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When we design using a hardware description language (HDL), these logical expressions and functions need to be mapped onto the low level logic blocks on an FPGA. In order to do this, we need to carry out three specific functions:
1. Mapping: Logic functions mapped onto CLBs.
2. Placement: CLBs placed on FPGA.
3. Routing: Routed connections between CLBs.
It is clearly becoming impossible to design “by hand” using today’s complex designs; we therefore rely on synthesis software to turn our HDL design description into the logic functions that can be mapped onto the FPGA CLBs. This design flow is an iterative process including optimization and implies a complete design flow. This will be discussed later in this book in much more detail. One of the obvious aspects of FPGA design that must be considered, however, is that of the available resources.
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