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Each transceiver channel contains one ring-based channel PLL ( CPLL ). The internal channel clocking architecture is shown in Fig. 4.2 . The TX and RX clock dividers can individually select the clock from the QPLL or CPLL to allow the TX and
Fig. 4.2 Internal channel clocking architecture
Fig. 4.3 CPLL block diagram
RX datapaths to operate at asynchronous frequencies using different reference clock inputs.
The CPLL outputs feed the TX and RX clock divider blocks, which control the generation of serial and parallel clocks used by the PMA and PCS blocks. The CPLL can be shared between the TX and RX datapaths if they operate at line rates that are integral multiples of the same VCO frequency. Figure 4.3 illustrates a conceptual view of the CPLL architecture. The input clock can be divided by a factor of M before feeding into the phase frequency detector. The feedback dividers, N1 and N2 , determine the VCO multiplication ratio and the CPLL output frequency. A lock indicator block compares the frequencies of the reference clock and the VCO feed- back clock to determine if a frequency lock has been achieved.
Each Quad contains one/two LC-based PLLs, referred to as the Quad PLLs ( QPLL0 and QPLL1 ). Either QPLL can be shared by the serial transceiver channels within the same Quad but cannot be shared by channels in other Quads . Use of QPLL0/QPLL1 is required when operating the channels at line rates above the CPLL operating range. The GTHE3_COMMON/GTHE2_ COMMON primitive encapsulates both the GTH QPLLs and must be instantiated when either QPLL is used. The QPLL0/QPLL1 out- puts feed the TX and RX clock divider blocks of each serial transceiver channel within the same Quad , which control the generation of serial and parallel clocks used by the PMA and PCS blocks
Fig. 4.4 QPLL block diagram
Figure 4.4 illustrates a conceptual view of the QPLL0/QPLL1 architecture. The input clock can be divided by a factor of M before it is fed into the phase frequency detector. The feedback divider N determines the VCO multiplication ratio. The QPLL0/QPLL1 output frequency is half of the VCO frequency. A lock indicator block compares the frequencies of the reference clock and the VCO feedback clock to determine if a frequency lock has been achieved.
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