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One of the biggest advantages of the Vivado Design Suite is the Xilinx IP are all deliv- ered as HDL, enabling fast behavioral simulation. The HDL fi les needed for simula- tion are created during the generation of the output products. The fi les are all located in the IP folder or within the Core Container fi le. When using the Core Container , the simulation-related fi les are copied into the ip_user_fi les directory.
hen using a Vivado RTL project and launching simulations from the GUI, all fi les required for simulating the IP are automatically sent to the simulator along with your HDL fi les. In addition to the integrated Vivado simulator ( XSIM ), Vivado can launch specifi c simulators from third parties. Chapter 11 covers more on simulation.
If you elect to simulate outside of the Vivado Design Suite, scripts are provided in the ip_user_fi les directory for each supported simulator. These scripts will reference IP fi les either from the IP directory or the ip_user_fi les as applicable depending on if you are using Core Container or not. The IP scripts can be incorpo- rated into your own simulation scripts.
You can also use the export_simulation command to create a script to simulate your entire design, including the IP. The command can also copy all the simulation HDL fi les into the directory of your choice. This makes it very easy to start simulating your design.
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