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Using an IP is straightforward. If the IP was created in an RTL project, then simply use the provided instantiate template for either VHDL or Verilog to instantiate the IP in your design. The template is found in the IP Sources tab for the specifi c IP. If not using the Vivado GUI, the instantiation template can be found in the following locations:
• The IP directory
• In the < project name>.ip_user_files (IP created in an RTL project) or the ip_ user_files directory (IP created in a Managed IP project)
If scripting your flow, read the IP using the readip command and pass the < ip_name >.xci or <ip_name>xcix . By referencing the XCI/XCIX fi le, Vivado will pull all required files in as needed, including HDL, DCP (if IP synthesized out-of- context ), constraints, etc. If scripting a non-project fl ow, the IP must be fully generated.
Though you can use the IP DCP file in your flow, it is strongly recommended you use the XCI/XCIX . The reasons are:
• You can track the state of the IP going forward and can upgrade if you desire.
• During implementation, the IP XDC files will be processed in context of the entire netlist (see Sect. 3.6 for more details).
• If needed, you can make changes to the IP HDL (e.g., modify clocking resources).
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