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Once you have customized your IP, it is recommended that you generate all the fi les that are needed by Vivado to make use of this IP. The generation of many IP can be done in parallel, including the synthesis of IP.
Generating output products or generating IP refers to these two stages (Fig. 3.4 ):
• Copying the IP fi les from the Vivado installation area
• Vivado processing the IP
– Produce HDL based upon the customization options specifi ed by the user.
– Synthesize IP stand-alone (default).
– Create simulation scripts for the IP for all supported simulators.
There are two options for synthesis of the IP at the end of customizing when presented with the Generate Output Products window (Fig. 3.4 ):
Fig. 3.4 Generate output products
• Global : The HDL fi les are created at this stage. However, the IP is synthesized along with the user HDL each time the design is synthesized.
• Out-of-context per IP (default): The IP is synthesized at this stage, just one time. During synthesis of the design the IP is seen as a black box. Later, during imple- mentation, the netlist for all the IP will be combined with the top level netlist. This can greatly reduce the top level synthesis runtime during development.
There is no compelling reason to synthesize the IP globally. Since the Vivado tool places a DONT_TOUCH on the IP during synthesis, there are no cross bound- ary optimizations performed (explained in Sect. 3.6.2 ). Any cross boundary optimizations, such as propagation of constants, will be performed during implementation.
Xilinx IP source fi les are delivered in the installation directory of the Vivado Design Suite. The IP consist of HDL (much of it encrypted) as well as scripts. The options specified during customization are processed by the scripts and HDL fi les are produced. Part of generation consists of copying all the static HDL fi les as well as the script-generated HDL fi les to the IP directory specifi ed during IP customization.
Depending on the specifi c IP, different fi les will be copied from the install area to the user-specifi ed IP folder (or to within the Core Container fi le) during genera- tion. Possible types of fi les include:
• Static RTL fi les
• RTL fi les produced by scripts
• Instantiation templates
• Constraints
• Simulation fi les
• Testbench fi les
• Change log
Once this stage is completed, Vivado creates simulation scripts for all the sup- ported simulators and places these scripts in the ip_user_fi les folder ( Managed IP project) or <project_name>.ip_user_fi les (if IP created in a regular RTL project).
The Core Container is a compressed binary fi le version of the IP folder (. xcix ). Vivado will read directly (not unzip to a temporary location) from the core con- tainer the fi les needed for synthesis, simulation, and implementation. Using this feature greatly reduces the number of fi les on disk needed for the IP. The Core Container is a standard ZIP fi le and can be opened with an appropriate utility, though modifying any of the contents is not supported and will likely cause issues with the use of the fi le.
To enable the Core Container for all new IP, go to the Project Settings → IP→ General tab and check the box Use Core Containers for IP . Alternatively, you can enable or disable the Core Container feature on a per IP basis. Select the IP in the IP Sources view, right click, and select Enable Core Container to enable. If enabled, you can right click and select Disable Core Container . This will switch between the IP being a folder on disk or an XCIX fi le and vice versa.
The Core Container is a complete representative of the IP you customized. All the fi les needed for Vivado are contained within. If using a project, the view of the IP will be identical regardless of using Core Container or not. You can open unen- crypted HDL and constraint fi les, which will be listed in the IP Source view exactly the same as if not using Core Container. If outside of the Vivado project GUI, sup- port fi les such as the instantiation template and simulation fi les can be extracted from the Core Container using the export_ip_user_fi les command. This will place them in the ip_user_fi les directory.
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Product Categories: FPGAs
Lifecycle:Active Active
RoHS: No RoHS
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