This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Technical Tutorials > Designing with Xilinx FPGAs Using Vivado > IP Flows > IP Customization

TABLE OF CONTENTS

Xilinx FPGA FPGA Forum

IP Customization

FONT SIZE : AAA

Each IP has many confi guration options that can be set, for example, for a FIFO, width and depth, independent read and write clock, etc. (Fig. 3.2 ). A particular set of options for an IP is referred to as customization and will have a unique user- provided name. The customization options are encapsulated in the IP_name. xci fi le. Once an IP customization has been created, you can instantiate it in your design using the instantiation template (need to generate the output products to get this; see Sect. 3.4 ) as many times as required. Creating an IP customization does not add it to your design; you must instantiate it in your RTL for it to be used. You can create multiple customizations of the same IP, each with differing confi guration options having a unique name. 

There are three ways in which to create an IP customization: 

• Managed IP Project (recommended) 

• Directly from within a Vivado RTL project 

• Using Tcl script 

Example of an IP customization GUI.png

Fig. 3.2 Example of an IP customization GUI



Fig. 3.3 Icon for creating or opening a managed IP project 

Icon for creating.png













Managed IP Project

It is recommended when working with IP that you use a Managed IP project. This is a special Vivado project specifi cally for creating IP customizations. The same IP Catalog found in a Vivado RTL Project is provided to search for and customize IP. Each IP created is kept in its own folder with the user-provided name used during the customization. If you elect to use the Core Container feature (explained in Sect. 3.4.3 ), a single compressed binary fi le with the name given during customiza- tion with the extension of .xcix will be present. The IP folder or Core Container fi le are stored outside of the Managed IP Project directory. The IP folder or Core Container fi le can be copied into a revision control system along with other design sources. If electing to use a folder for the IP, it is recommended that you place the entire folder and all contents into revision control. 

From the starting page of Vivado, select Manage IP (Fig. 3.3 ). You can either specify a new location on disk for a Managed IP Project or open an existing location. 

Within a Project

You can elect to create IP customizations from directly within an RTL project. From the Flow Navigator , select IP Catalog and search/browse for the desired IP. During customization, by default the IP and associated fi les will be stored in the Vivado project directory structure. You can change this by the IP Location button, allowing you to specify a directory of your choice. This allows you to save the IP and its associated fi les outside of the Vivado project directory, similar as a Managed IP Project does. This is recommended when working with revision control systems. 

Tcl Script

When creating an IP customization, Tcl commands are executed to create the IP and to apply the various options specifi ed during customization. You can add these Tcl commands to your custom Make or script fl ow to create the IP on the fl y. To compile your design, you would read in your RTL source, create the IP with Tcl commands, and proceed to synthesize or implement. The downside to this approach is that each time you build your project, the IP will have to be created and generated, which can be time consuming if there are many IP being used. Also, if the script was created with a previous version of Vivado, the IP might have changed the customization options which can result in errors being encountered. 

  • XC3S400-4FGG320I

    Manufacturer:Xilinx

  • FPGA Spartan-3 Family 400K Gates 8064 Cells 630MHz 90nm Technology 1.2V 320-Pin FBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

    RoHS:

  • XC5204-6PQ160C

    Manufacturer:Xilinx

  • FPGA XC5200 Family 6K Gates 480 Cells 83MHz 0.5um Technology 5V 160-Pin PQFP
  • Product Categories: Semiconducteurs & Actifs

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC5204-6TQ144C

    Manufacturer:Xilinx

  • FPGA XC5200 Family 6K Gates 480 Cells 83MHz 0.5um Technology 5V 144-Pin TQFP EP
  • Product Categories: FPGA

    Lifecycle:Obsolete -

    RoHS: No RoHS

  • XC2S50-5PQ208I

    Manufacturer:Xilinx

  • FPGA Spartan-II Family 50K Gates 1728 Cells 263MHz 0.18um Technology 2.5V 208-Pin HSPQFP EP
  • Product Categories: Voltage regulator tube

    Lifecycle:Active Active

    RoHS: No RoHS

  • XC3S400-5FGG320C

    Manufacturer:Xilinx

  • FPGA Spartan-3 Family 400K Gates 8064 Cells 725MHz 90nm Technology 1.2V 320-Pin FBGA
  • Product Categories: FPGAs (Field Programmable Gate Array)

    Lifecycle:Active Active

    RoHS:

Need Help?

Support

If you have any questions about the product and related issues, Please contact us.