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The first type of device to be programmable was the Programmable Array Logic (PAL) with a typical layout as shown in Figure 2.1. This consists of an array of logic gates that could be connected using an array of connections. These devices could support a small number of flip-flops (usually <10) and were able to implement small state machines. These devices still have a use for specific functions on a small scale, but clearly will be limited for more complex applications. They are, however, still useful for low-cost and compact solutions to a specific digital design requirement.
Complex Programmable Logic Devices (CPLD) such as shown in Figure 2.2 were developed to address the limitations of simple PAL devices. These devices used the same basic principle as PALs, but had a series of macro blocks (each roughly equivalent to a PAL) that were connected using routing blocks. With, in some cases, many thousands of logical elements, the CPLD can be extremely useful for implementing a programmable device with custom logic functions and state machines. In some ways, the latest CPLD and early FPGA devices are almost indistinguishable, with one crucial difference. The CPLD is a fixed array of logic, but the FPGA uses complex logic blocks (discussed in the next section of this chapter). However, CPLDs are still of a relatively small scale, and the modern reconfigurable device of choice for high performance is the FPGA.
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