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The preceding counter example illustrates how easy it is to define some hardware in Verilog. However, it is missing an important feature that you will find in almost any Verilog example that you would care to look at. That is, it is not synchronized with a clock.
The example works, but only because it is so simple. The problem that arises, as soon as projects become even slightly more complex than this, is that signals take different times to propagate through logic gates, and this means that an output that depends on inputs from many other parts of the system and possibly even the output itself will take time to settle to its final value. It may have glitchy pulses that should be ignored by other parts of the system. Such outputs are described as metastable.
This is why you will have seen some warning messages as you built the project, not least because the clock input to the counter appears to ISE as a synchronizing clock input, but we are just using it as a general input connected to a switch.
The solution to this problem of metastable outputs is to use a system-wide clock (usually tens of megahertz). Everything then happens each time the clock ticks. This means that any metastable outputs will have had time to settle before their value is sampled. The <= operator that you used in the counter example in preference to = ensures that all assignments using <= within an always block happen at the same time (in the same clock cycle.) This gives time for all the outputs in the system to settle well before the next clock cycle occurs.
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