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As mentioned above, clock skew should be minimized to an acceptable level. The main contributors to clock skew are jitter in the source signal, and noisy power supply and signal environment. To minimize these negative effects, special care must be paid to the signal propagation on the boards and across boards including
• Consistent impedance of all clock signals is critical.
• Proper routing on the board will reduce cross-talk with other signals.
• Well regulated power supplies with low-impedance paths to all loads.
• Trace length and delay matching for most likely parallel data and clock paths e.g., from an FPGA to its dedicated IO connector.
• There are other sources for understanding the issues on board layout and signal integrity (see references). This is not a manual for PCB layout and design and we only mention it here as a reminder that creating a large multi-FPGA board is a challenging problem, although not insurmountable with access to the right PCB-layout expertise.
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Manufacturer:Xilinx
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Manufacturer:Xilinx
Product Categories: Embedded - CPLDs (Complex Programmable Logic Devices)
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