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FPGA configuration is the process in which the FPGAs are programmed with a bit stream and take on our intended functionality. Configuration data, which can range in the tens of Mbits per FPGA, is generated by the FPGA tools after place & route is completed.
Since FPGAs are SRAM-based volatile devices, the configuration process must take place after each power-up, but can also be performed an unlimited number of times after initial configuration.
There are a number of methods to configure FPGAs that can be broadly described as parallel or serial, master or slave, and JTAG. The mode is determined by hardwiring dedicated configuration mode signals. The following list describes the major characteristics of the different configuration modes:
• In the master modes, the FPGA is controlling the configuration upon power-up or when triggered by a configuration pin.
• In slave modes an external device controls the configuration interface.
• Serial configuration is slower than parallel but uses less signals, therefore leaving more signals to be used for the application itself.
• JTAG interface overrides and other configuration modes.
Configuration data can reside in a non-volatile memory or at a host computer. Multiple bit streams can be placed sequentially in the storage device and all FPGAs are configured in order in a sequence determined by hardwiring each FPGA.
The most common configuration mode is via JTAG and this is usually how the download cables form host PC’s communicates with the devices. However, it would be non-intuitive for those not familiar with FPGAs to make use of that download cable approach.
For non-FPGA experts, we can employ some added dedicated circuitry and common CompactFLASH™ (CF) cards. Commercial CF devices are readily available and of high enough capacity to hold the configuration data of even the largest FPGA devices. In fact, multiple configurations can be stored in the same card and the end-users can choose which one is loaded on the board by a simple setting of switches or even by remote control from a utility running on a host PC in the lab. There would still be room left over in the CF memory to hold other data, for example, documentation and user guides. This approach is very popular with those creating multiple copies of the FPGA platform for distribution to remote end-users. Removable CF cards provide the flexibility to transport the systems configuration to remote locations.
To enable the use of CF cards, a dedicated circuit called the Xilinx ® System ACE™ controller is typically implemented in a separate small FPGA on the board. System
ACE technology is a piece of Xilinx ® IP which reads the CF card and then emulates a JTAG interface memory for the FPGAs to be configured. Figure 58 shows a multi-mode configuration approach centered upon the System ACE controller.
Figure 58: CompactFLASH™ based configuration via System ACE™ technology
More information about System ACE and for a full description of FPGA configuration modes, refer to Xilinx ® documentation listed in the references.
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