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System-Level IP-Focused Design with Vivado
One of the major factors in modern systems design is the potential for design reuse and rapid development. Time to market is critical in many application areas, and design tools that accelerate the development process, crucially without compromising the robustness of the verification stage or quality of results, bring clear advantages.
The Vivado design flow is based on these principles, and is built on the premise that many system building blocks are exactly that — ready pieces of IP that can be integrated into a project. Unlike older design methods, which typically cater for building systems entirely from the ground up, Vivado focuses instead on exploiting the pre-verified IP available in the Vivado libraries (i.e. cores developed by Xilinx), third party IP developers, or the previous exertions of the designer (and his or her team). To a large extent, the focus of the task has shifted upwards to system integration, rather than low-level hardware design, and the features of the Vivado Design Suite reflect this. Having said that, there is also scope for undertaking custom logic design if the system calls for it.
IP Integrator, used to design the example system shown in Figure 3.4, is the primary embodiment of this IP-focused design method. IP Integrator is a feature of the Vivado Design Suite, with which the designer is able to adopt the same ‘top-down’ approach they would naturally take in conceiving the system hierarchy. IP instances can either be introduced from the existing catalogue where appropriate, or created as black boxes for later population with functional subsystems, and the interfaces between these various elements established. This approach lends itself to rapid development of the hardware system.
An example of IP instantiation is provided in Figure 3.6, which shows a view of the Vivado IP catalogue (note that only a small selection of IPs are visible). Here, a CoOrdinate Rotation DIgital Computer (CORDIC) IP has been selected and dragged into the workspace, or ‘canvas’. Following this, the designer would then configure the parameters of the CORDIC design unit, as shown in Figure 3.7, and connect it to other blocks as appro priate to the system being created.
The success of the IP integration stage relies on consistent behaviour and interfacing of IPs. To support this, the Vivado Design Suite includes a related feature, IP Packager, that enables IP to be consolidated into standard packages (based on the IP-XACT standard) with the aim of facilitating future design reuse. This is the recommended practice for IP developers and design teams to adopt; in this way, IP designs are made maximally portable
and reusable. From a design team perspective, building up an in-house repository of easily reusable IP, shared across the organisation, is a compelling method of accelerating product design cycles. IP Packager will be featured in detail in Chapter 18.
There are several tools and design creation techniques that can be used to generate IPs. For example, they may be coded from a HDL such as VHDL or Verilog; generated from a high-level C description by the Vivado HLS tool; or from a System Generator block diagram. These methods will be explored further in Chapter 13.
As a final note on Vivado, it should be highlighted that, although we predominantly feature the GUI aspect of the tools in this book, all of the design tasks may also be undertaken using the industry standard Tool Command Language (TCL) scripting language. This represents a very powerful, repeatable and parameterisable method of driving the design tools.
Manufacturer:Xilinx
Product Categories: FPGAs
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Manufacturer:Xilinx
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Manufacturer:Xilinx
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Manufacturer:Xilinx
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Manufacturer:Xilinx
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