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Home > FPGA Technical Tutorials > Design Recipes for FPGAs Using Verilog and VHDL > Design Automation of FPGAs > Place and Route

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Xilinx FPGA FPGA Forum

Place and Route

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There are two main techniques to place and route in current commercial software: which are recursive cut and simulated annealing.

Recursive Cut

In a recursive cut algorithm, we divide the netlist into two halves, and move devices between halves to minimize the number of wires that cross cut (while keeping the number of devices in each half the same). This is repeated to get smaller and smaller blocks. 

Simulated Annealing

The simulated annealing method Laarhoven [9] uses a mathematical analogy of the cooling of liquids into solid form to provide an optimal solution for complex problems. The method oper- atesontheprinciplethatannealedsolidswillfindthelowestenergypointatthermalequilibrium and this is analogous to the optimal solution in a mathematical problem. The equation for the energy probability used is defined by the Boltzmann distribution given by Equation (5.1): 


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where Z(T) is the partition function, which is a normalization factor dependent on the temperature T, k B is the Boltzmann constant, and E is the energy. This equation is modified into a more general form, as given by (5.2), for use in the simulated annealing algorithm.

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where Q(c) is a general normalization constant, with a control parameter c, which is analogous to temperature in Equation (5.1). C(i) is the cost function used, which is analogous to the energy in Equation (5.1). The parameters to be optimized are perturbed randomly, within a distribution, and the model tested for improvement. This is repeated with the control parameter decreased to provide a more stable solution. Once the solution approaches equilibrium, then the algorithm can cease. A flowchart of the full algorithm applied is given in Figure 5.4. 

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