Physical Design Flow

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Synthesis generates a netlist of devices plus interconnections. The Place and Route software figures out where the devices go and how to connect them. The results are not as good as you’d perhaps like: a 40-60% utilization of devices and wires is typical. The designer can trade off run time against greater utilization to some degree, but there are serious limits. Typically the FPGA vendor will provide a software toolkit (such as the Xilinx Design Navigator, or Altera’s Quartus ® II tools) that manages the steps involved in physical design. Regardless of the particular physical synthesis flow chosen, the steps required to translate the VHDL or EDIF output from an RTL Synthesis software program into a physically downloadable bit file are essentially the same and are listed here:

1. Translate

2. Map

3. Place

4. Route

5. Generate accurate timing models and reports

6. Create binary files for download to device

XC4VSX25-10FFG668C

Manufacturer:Xilinx
FPGA Virtex-4 SX Family 23040 Cells 90nm Technology 1.2V 668-Pin FCBGA
Product Categories: FPGAs

Lifecycle:Active Active

RoHS:

XC4VSX25-11FFG668C

Manufacturer:Xilinx
FPGA Virtex-4 SX Family 23040 Cells 90nm Technology 1.2V 668-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS:

XC2018-70PC84C

Manufacturer:Xilinx
LOGIC CELL ARRAY Field Programmable Gate Array
Product Categories:

Lifecycle:Obsolete -

RoHS: No RoHS

XC4VSX35-11FFG668C

Manufacturer:Xilinx
FPGA Virtex-4 SX Family 34560 Cells 90nm Technology 1.2V 668-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS:

XC3042-100PG84M

Manufacturer:Xilinx
FPGA XC3000 Family 3K Gates 144 Cells 100MHz 5V 84-Pin CPGA
Product Categories:

Lifecycle:Obsolete -

RoHS: No RoHS

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