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Register Transfer Level (RTL) VHDL is the input to most standard synthesis software tools. The VHDL must be written in a form that contains registers, state machines (FSM), and combinational logic functions. The synthesis software translates these blocks and functions into gates and library cells from the FPGA library. The RTL design flow is shown in Figure 5.3. Using RTL VHDL restricts the scope of the designer as it precludes algorithmic design, as we shall see later. This approach forces the designer to think at quite a low level, making the resulting code sometimes verbose and cumbersome. It also forces structural decisions early in the design process, which can be restrictive and not always advisable, or helpful.
The design process starts from RTL (Register Transfer Level) VHDL, as follows:
• Simulation (RTL): needed to develop a test bench (VHDL).
• Synthesis (RTL): targeted at a standard FPGA platform.
• Timing Simulation (Structural) simulate to check timing.
• Place and Route using standard tools (e.g., Xilinx Design Manager).
Although there are a variety of software tools available for synthesis (such as LeonardoSpectrum™ or Synplify), they all have generally similar approaches and design flows.
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