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The basic HDL design flow is shown in Figure 5.3 and, as can be seen from this figure, synthesis is the key stage between high level design and the physical place and route which is the final product of the design flow. There are several different types of synthesis ranging from behavioral, to RTL and finally physical synthesis.
Behavioral synthesis is the mechanism by which high-level abstract models are synthesized to an intermediate model that is physically realizable. Behavioral models that are not directly synthesizable can be written in VHDL and so care must be taken with high-level models to ensure that this can take place, in fact. There are limited tools that can synthesize behavioral VHDL and these include the Behavioral Compiler from Synopsys, Inc. and MOODS, a research synthesis platform from the University of Southampton.
RTL (Register Transfer Level) synthesis is what most designers call synthesis, and is the mechanism whereby a direct translation of structural and register level VHDL can be synthesized to individual gates targeted at a specific FPGA platform. At this stage, detailed timing analysis can be carried out and an estimate of power consumption obtained. There are numerous commercial synthesis software packages, including Design Compiler ® , and Synplify ® , but this is not an exhaustive list as there are numerous offerings available at a variety of prices.
Physical synthesis is the last stage in a synthesis design flow and is where the individual gates are placed (using a floor plan) and routed on the specific FPGA platform.
Synthesis basically transforms program-like VHDL into a true hardware design (netlist). It requires a set of inputs, a VHDL description, timing constraints (when outputs need to be ready, when inputs will be ready, data to estimate wire delay), a technology to map to (list of available blocks and their size/timing information) and information about design priorities (area vs. speed). For big designs, the VHDL will typically be broken into modules and then synthesized separately. 10K gates per module was a reasonable size in the 1990s; however, tools can handle a lot more now.
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