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A typical HDL such as Verilog or VHDL as a language on its own is actually very limited in the breadth of the data types and primitive models available. As a result, libraries are required to facilitate design reuse and standard data types for model exchange, reuse, and synthesis. The primary library for standard VHDL design is the IEEE library. Within the IEEE Design Automation Standards Committee (DASC), various committees have developed libraries, packages, and extensions to standard VHDL. Some of these are listed below:
• IEEE Std 1076 Standard VHDL Language
• IEEE Std 1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
• IEEE Std 1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support
• IEEE Std 1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL)
• IEEE Std 1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)
• IEEE Std 1076.2 IEEE Standard VHDL Mathematical Packages (math)
• IEEE Std 1076.3 Standard VHDL Synthesis Packages (vhdlsynth)
• IEEE Std 1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
Each of these working groups consists of volunteers who come from a combination of academia, EDA industry and user communities, and collaborate to produce the IEEE Standards (usually revised every 4 years).
In order to use a library, first the library must be declared: library ieee; for each library. Within each library a number of VHDL packages are defined, which allow specific data types or functions to be employed in the design. For example, in digital systems design, we require logic data types, and these are not defined in the basic VHDL standard (1076). Standard VHDL defines integer, Boolean, and bit types, but not a standard logic definition. This is obviously required for digital design and an appropriate IEEE standard was developed for this purpose, IEEE 1164. It is important to note that IEEE Std 1164 is NOT a subset of VHDL (IEEE 1076), but is defined for hardware description languages in general.
In order to use a particular element of a package in a design, the user is required to declare their use of a package using the USE command. For example, to use the standard IEEE logic library, the user needs to add a declaration after the library declaration as follows:
1 use ieee.std_logic_1164.all;
The std_logic_1164 package is particularly important for most digital designs, especially for FPGA, because it defines the standard logic types used by ALL the commercially available simulation and synthesis software tools and is included as a standard library. It incorporates not only the definition of the standard logic types, but also conversion functions (to and from the standard logic types) and also manages the conversion between signed, unsigned, and logic array variables.
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