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Home > FPGA Technical Tutorials > Introduction to CPLD and FPGA Design > SIMULATION ISSUES > Static Timing Analysis

Static Timing Analysis

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Static timing analysis is a process that looks at a synchronous design and  determines the highest operating frequency of the design which does not  violate any setup and hold times. You can also use the static timing analysis  software to specify a specific frequency, and the tool will list all paths that  violate the timing requirements. These paths can then be adjusted to meet  your requirements. Any asynchronous parts of your design (they should be few,  if any) must be examined by hand.

Static timing analysis, or some sort of timing analysis must be performed  immediately before layout of your chip. At this point, the timing numbers will  be estimates that take expected trace lengths into account. After layout, timing  analysis must be performed again to determine that the real chip, with real  trace lengths and delays, still meets you timing requirements.


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