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Home > FPGA Technical Tutorials > Introduction to CPLD and FPGA Design > DESIGN FOR TEST (DFT) > Signature Analysis

Signature Analysis

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Signature analysis involves putting a pseudo-random sequence of ones and  zeroes into the chip and noting the ones and zeroes that come out. This output  sequence is referred to as the chip’s signature. This type of testing can be  accomplished with the chip in a normal mode of operation, but is usually  performed in scan mode as described above. By repeating the same pseudorandom series of bits, the resulting signature should be the same for each chip.  Any chip that produces an incorrect signature is a bad chip. This type of testing  is probabilistic and assumes that a pseudo-random sequence of events has a  good chPerhaps the most important phase of chip design, and the most often  overlooked phase, is that of simulation. Simulation can save many frustrating  hours debugging a chip in your system. Doing a good job at simulation uncovers  errors before they are set in silicon, and can help determine that your chip will  function correctly in your system. ance of catching errors, which may not be true. However, it requires  very little hardware to implement and can be used as a simple form of BIST.

There are two main aspects of your design for which simulation is used  to determine correctness - functionality and timing. Functionality refers to how  the chip functions as a whole, and how it functions in your system. A chip  which is designed to function as an Ethernet controller may function correctly  on its own. In a system that requires an ATM controller, for example, it will not  work at all. It is important to look not only at the functionality of the chip as an  independent design, but also to test its functionality within the system in which  it will be incorporated.

The second aspect of your design which simulation examines is timing.  Will your chip meet all of its timing requirements under all possible conditions?  Are there any race conditions? Are the setup and hold time requirements met  for each flip-flop? Do the I/O signals of the chip meet the timing requirements  of the system? The following sections discuss ways of using timing to determine  both correct functionality and correct timing.


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