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When we define the module behavior there are several ways in which this can be done. Verilog is in nature a “bottom up” style language and therefore we need to think in terms of assigning signals directly, or acting in terms of hardware “blocks.” The two types of behavioral block that we will consider first are the always and initial blocks.
The always block is a way of defining a section of code that will always be activated—in other words the same as a VHDL process, it is a block of hardware that is always active. The initial block, in contrast, is activated on startup, and used to initialize conditions, then never used again.
In order to illustrate how this works in practice we can consider our simple counter. The basic behavior of this module is to count on a rising clock edge, and increment the counter by one, unless the reset is high, in which case the output value will be set to zero.
The basic outline of the always block is as shown here
1 always @ ( posedge clk ) / Count on the Rising Edge of the Clock
2 begin: counter / Start of the Count − block name count
3
4 / Count Code
5
6 end / End of the Count − end of block counter
If we look at this code, we can see that the always keyword is used to define the block and that it is activated by the function posedge—in other words the rising edge of the clk clock signal. The code is contained between a begin and end, with the name after the begin defining a block name—which is useful in complex designs for the identification of specific signals within blocks.
The final step in the development of our counter is to therefore define the behavior, and implement the check for reset active high and the counter itself.
1 module counter (
2 clk, / Clock Signal (Rising Edge)
3 rst, / reset Signal (Active High)
4 dout / Counter Output (7:0)
5 );
6 / port declarations
7 input clk;
8 input rst;
9 output [7:0] dout;
10
11 / wire definitions
12 wire clk;
13 wire rst;
14
15 / Register definitions
16 reg [7:0] dout;
17
18 always @ ( posedge clk ) / Count on the Rising Edge of the Clock
19 begin: COUNTER / Start of the Counter − block name COUNTER
20
21 if (rst == 1’b1) begin
22 dout <= #1 8’b00000000;
23 end
24 else begin
25 dout <= #1 dout + 1;
26 end
27
28 end / End of the Counter − end of block COUNTER
29
30 endmodule
Manufacturer:Xilinx
Product Categories: CPLDs (Complex Programmable Logic Devices)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: CPLDs
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
RoHS: No RoHS
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