Wires and Registers

Wires and Registers

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Once a module has been declared and its ports defined, it is then necessary to make those available internally to the module for use as connections. The most basic connection type is called a wire and this is exactly as its name suggests, simply a direct connection.

If we take our counter example, in order to make each port available for internal coding, we need to setup a wire for each input. These are defined using the wire keyword and the extended module is given as follows:

1 module counter (

2 clk, / Clock Signal (Rising Edge)

3 rst, / reset Signal (Active High)

4 dout / Counter Output (7:0)

5 );

6 / port declarations

7 input clk;

8 input rst;

9 output [7:0] dout;

11 / wire definitions

12 wire clk;

13 wire rst;

15 /contents of the model here

17 endmodule

But what about the counter output? Why did we not simply assign a wire type to the dout variable? The answer is that wire is essentially combinatorial (i.e., a direct connection) whereas the output is synchronous and needs to be held in a register. In Verilog we denote this using the reg keyword rather than the simple wire and so the dout variable needs to be defined as shown below. Notice that the declaration of the register also needs to have the bus defined in an identical manner to the port declaration.