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Once we have a basic module definition (with a name) the next step is to connect it up. Consider the example of an 8-bit counter that has a clock (clk) and reset (rst) input, with the output word defined as dout (7 down to 0) The module definition needs to be modified to include the names of the ports in the header as shown here:
1 module counter (clk,rst,dout);
2
3 /contents of the model here
4
5 endmodule
The module can also be written with the port names spread over several lines such as:
1 module counter (
2 clk,
3 rst,
4 dout
5 );
6
7 /contents of the model here
8
9 endmodule
The obvious question is “why would we do that?” However, this way makes it simple to add descriptive comments next to each port name definition, which can be extremely helpful in debugging the model.
Comments in Verilog use the / notation (the same as in C++) and so we could write the module header with some additional comments as shown below. As you can see, we can put helpful comments such as the active clock edge (rising or falling), whether the reset signal is active high or low, and finally the width of the dout variable.
1 module counter (
2 clk, / Clock Signal (Rising Edge)
3 rst, / reset Signal (Active High)
4 dout / Counter Output (7:0)
5 );
6
7 /contents of the model here
8
9 endmodule
The final step at this point of model creation is to define the type of the ports, in terms of direction. For example, are they inputs, outputs or both? Also, what is the width of the bus if they are composite (multiple value) ports? In this simple example, the clk and rst ports are both inputs, and the dout port is an output, of width 8 (tagged with indices 7 down to 0 in classical digital designer format).
This definition is done using the keywords input, output or inout and the expanded port definitions are given here.
1 module counter (
2 clk, / Clock Signal (Rising Edge)
3 rst, / reset Signal (Active High)
4 dout / Counter Output (7:0)
5 );
6 / port declarations
7 input clk;
8 input rst;
9 output [7:0] dout;
10
11 /contents of the model here
12
13 endmodule
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