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Home > FPGA Technical Tutorials > FPGAs: World Class Designs > FPGA vs. ASIC Designs > STATE MACHINE ENCODING

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Xilinx FPGA FPGA Forum

STATE MACHINE ENCODING

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The encoding scheme used for state machines is a good example of an area  where what’s good for an ASIC design might not be well suited for an FPGA  implementation.   

As we know, every LUT in an FPGA has a companion flip-flop. This   usually means that there are a reasonable number of flip-flops sitting around  waiting for something to do. In turn, this means that in many cases, a “ one-hot ”  encoding scheme will be the best option for an FPGA-based state machine,  especially if the activities in the various states are inherently independent.

Key Concept  

The “ one-hot ” encoding scheme refers to the fact that each state in a state  machine has its own state variable in the form of a flip-flop, and only one state  variable may be active ( “ hot ” ) at any particular time.

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