PIPELINING AND LEVELS OF LOGIC

PIPELINING AND LEVELS OF LOGIC

FAQ  

What is pipelining?  

One tends to hear the word pipelining quite a lot, but this term is rarely explained  in a clear way. Pipelining can be compared to an assembly line used in manufacturing automobiles. Assume that different specialists are needed for each step of  the process: someone to attach the wheels to the chassis, the engine to the chassis,  the body to the chassis, and paint the whole thing. It would be highly inefficient  and time-consuming for all these specialists to sit around waiting for their turn to  do their job. Instead, several cars are put on the assembly line at once, and each  specialist does his or her job as the car moves down the line. Once the assembly  line is in full flow, everyone will be working all the time and cars are created  much more quickly.

We can often replicate this scenario in electronics. Assume we have a  design (or a function forming part of a design) that can be implemented as a  series of blocks of combinatorial logic ( Figure 4-1 ). Let’s say that each block takes  Y nanoseconds to perform its task and that we have five such blocks (of which  only three are shown in Figure 4-1 , of course). In this case, it will take 5 Y  n anoseconds for a word of data to propagate through the function, starting with  its arrival at the inputs to the first block and ending with its departure from the  outputs of the last block. However, we can instead use a pipelined design technique in which “ islands ” of combinatorial logic are sandwiched between blocks  of registers.

Generally speaking, in the arrangement shown in Figure 4-1 , we wouldn’t  want to present a new word of data to the inputs until we have stored the output results associated with the first word of data. This means that we end up  with the same result as our inefficient car assembly scenario in that it takes a  long time to process each word of data, and the majority of the workers (logic  blocks) are sitting around twiddling their metaphorical thumbs for most of the  time. In the pipelined design technique shown in Figure 4-2 , all of the register  banks are driven by a common clock signal. On each active clock edge, the  registers feeding a block of logic are loaded with the results from the previous stage. These values then propagate through that block of logic until they  arrive at its outputs, at which point they are ready to be loaded into the next  set of registers on the next clock. In this case, as soon as “ the pump has been  primed ” and the pipeline is fully loaded, a new word of data can be processed  every Y nanoseconds. 

Generally speaking, in the arrangement shown in Figure 4-1 , we wouldn’t  want to present a new word of data to the inputs until we have stored the out put results associated with the first word of data. This means that we end up  with the same result as our inefficient car assembly scenario in that it takes a  long time to process each word of data, and the majority of the workers (logic  blocks) are sitting around twiddling their metaphorical thumbs for most of the  time. In the pipelined design technique shown in Figure 4-2 , all of the register  banks are driven by a common clock signal. On each active clock edge, the  registers feeding a block of logic are loaded with the results from the previous stage. These values then propagate through that block of logic until they  arrive at its outputs, at which point they are ready to be loaded into the next  set of registers on the next clock. In this case, as soon as “ the pump has been  primed ” and the pipeline is fully loaded, a new word of data can be processed  every Y nanoseconds.

Levels of Logic   

All of this boils down to the design engineer’s having to perform a balancing act. Partitioning the combinational logic into smaller blocks and increasing  the number of register stages will increase the performance of the design, but  it will also consume more resources (and silicon real estate) on the chip and  increase the latency of the design.

This is also the point where we start to run into the concept of levels of  logic. For example, Figure 4-3 would be said to comprise three levels of logic  because the worst-case path involves a signal having to pass through three gates  before reaching the output.

In the case of an ASIC, a group of gates as shown in Figure 4-3 can be  placed close to each other such that their track delays are very small. This means  that, depending on the design, ASIC engineers can sometimes be a little sloppy  about this sort of thing (it’s not unheard of to have paths with, say, 15 or more  levels of logic).

By comparison, if this sort of design were implemented on an FPGA with  each of the gates implemented in a separate LUT, it would “ fly like a brick ”  (go incredibly slowly) because the track delays on FPGAs are much more significant, relatively speaking. In reality, of course, a LUT can actually represent several levels of logic (the function shown in Figure 4-3 could be implemented in a  single 4-input LUT), so the position isn’t quite as dire as it may seem at first.

Having said this, the bottom line is that in order to bring up (or maintain) performance, FPGA designs tend to be more highly pipelined than their ASIC counterparts. This is facilitated by the fact that every FPGA logic cell tends to comprise  both a LUT and a register, which makes registering the output very easy.

Key Concept  

One way to think of latency is to return to the concept of an automobile assembly line. In this case, the throughput of the system might be one car rolling off  the end of the line every minute. However, the latency of the system might be a  full eight-hour shift since it takes hundreds of steps to finish a car (where each of  these steps corresponds to a logic/register stage in a pipelined design).