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Like many other modern devices, today’s FPGAs are equipped with a JTAG port. Standing for the Joint Test Action Group and officially known to engineers by its IEEE 1149.1 specification designator, JTAG was originally designed to implement the boundary scan technique for testing circuit boards and ICs.
A detailed description of JTAG and boundary scan is beyond the scope of this book. For our purposes here, it is sufficient to understand that the FPGA has a number of pins that are used as a JTAG port. One of these pins is used to input JTAG data, and another is used to output that data. Each of the FPGA’s remaining I/O pins has an associated JTAG register (a flip-flop), where these registers are daisy-chained together ( Figure 3-9 ).
The idea behind boundary scan is that, by means of the JTAG port, it’s possible to serially clock data into the JTAG registers associated with the input pins, let the device (the FPGA in this case) operate on that data, store the results from this processing in the JTAG registers associated with the output pins, and, ultimately, to serially clock this result data back out of the JTAG port.
However, JTAG devices also contain a variety of additional JTAG-related control logic, and, with regard to FPGAs, JTAG can be used for much more than boundary scans. For example, it’s possible to issue special commands that are loaded into a special JTAG command register (not shown in Figure 3-9 ) by means of the JTAG port’s data-in pin. One such command instructs the FPGA to connect its internal SRAM configuration shift register to the JTAG scan chain. In this case, the JTAG port can be used to program the FPGA. Thus, today’s FPGAs now support five different programming modes and, therefore, require the use of three mode pins (additional modes may be added in the future).
Key Concept
Note that the JTAG port is always available, so the device can initially be configured via the traditional configuration port using one of the standard configuration modes, and it can subsequently be reconfigured using the JTAG port as required. Alternately, the device can be configured using only the JTAG port.
Key Concept
Note that the JTAG port is always available, so the device can initially be configured via the traditional configuration port using one of the standard configuration modes, and it can subsequently be reconfigured using the JTAG port as required. Alternately, the device can be configured using only the JTAG port.
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Product Categories: Memory - Configuration Proms for FPGA's
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