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The basic syntax for a simple if statement is as follows:
1 if (condition) then
2 −− statements
The condition is a Boolean expression, of the form a > b or a = b. Note that the comparison operator for equality is a single =, not to be confused with the double == used in some programming languages. For example, if two signals are equal, then setting an output high would be written in VHDL as:
1 if ( a = b ) then
2 out1 <= 1;
3 end if;
If the decision needs to have both the if and else options, then the statement is extended as follows:
1 if (condition) then
2 −− statements
3 else
4 −− statements
5 end if;
So in the previous example, we could add the else statements as follows:
1 if ( a = b ) then
2 out1 <= 1;
3 else
4 out1 <= 0;
5 end if;
And finally, multiple if conditions can be implemented using the general form:
1 if (condition1) then
2 −− statements
3 elsif (condition2)
4 −− statements
5 −− more elsif conditions & statements
6 else
7 −− statements
8 end if;
With an example:
1 if ( a > 10) then
2 out1 <= 1;
3 elsif( a > 5) then
4 out1 <= 0;
5 else
6 out1 <= 1;
7 end if;
As we have seen with the if statement, it is relatively simple to define multiple conditions, but it becomes a little cumbersome, and so the case statement offers a simple approach to branching, without having to use Boolean conditions in every case. This is especially useful
for defining state diagrams or for specific transitions between states using enumerated types.
An example of a case statement is:
1 case testvariable is
2 when 1 =>
3 out1 <= 1;
4 when 2 =>
5 out2 <= 1;
6 when 3 =>
7 out3 <= 1;
8 end case;
This can be extended to a range of values, not just a single value:
1 case test is
2 when 0 to 4 => out1 <= 1;
It is also possible to use Boolean conditions and equations. In the case of the default option (i.e., when none of the conditions have been met), then the term “when others” can be used:
1 case test is
2 when 0 => out1 <= 1;
3 when others => out1 <= 0;
4 end case;
The most basic loop in VHDL is the for loop. This is a loop that executes a fixed number of times. The basic syntax for the for loop is shown below:
1 for loopvar in start to finish loop
2 −− loop statements
3 end loop;
It is also possible to execute a loop that counts down rather than up, and the general form of this loop is:
1 for loopvar in start downto finish loop
2 −− loop statements
3 end loop;
A typical example of a for loop would be to pack an array with values bit by bit, for example:
1 signal a : std_logic_vector(7 downto 0);
2 for i in 0 to 7 loop
3 a(i) <= 1;
4 end loop;
Both the while and loop loops have an indeterminant number of loops, compared to the fixed number of loops in a for loop and as such are usually not able to be synthesized. For FPGA design, they are not feasible as they will usually cause an error when the VHDL model is compiled by the synthesis software.
The exit command allows a for loop to be exited completely. This can be useful when a condition is reached and the remainder of the loop is no longer required. The syntax for the exit command is shown below:
1 for i in 0 to 7 loop
2 if ( i = 4 ) then
3 exit;
4 endif;
5 endloop;
The next command allows a for loop iteration to be exited; this is slightly different from the exit command in that the current iteration is exited, but the overall loop continues onto the next iteration. This can be useful when a condition is reached and the remainder of the
iteration is no longer required. An example for the next command is shown below:
1 for i in 0 to 7 loop
2 if ( i = 4 ) then
3 next;
4 endif;
5 endloop;
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