USING THE CONFIGURATION PORT

The early FPGAs made use of something called the configuration port .  Even today, when more sophisticated techniques are available (like the JTAG  interface discussed later in this chapter), this method is still widely used  because it’s relatively simple and is well understood by stalwarts in the FPGA  fraternity.  
We start with a small group of dedicated configuration mode pins that are  used to inform the device which configuration mode is going to be used. In the  early days, only two pins were employed to provide four modes.

Note that the names of the modes shown in this table—and also the relationship between the codes on the mode pins and the modes themselves—are intended for use only as an example. The actual codes and mode names vary  from vendor to vendor.

The mode pins are typically hardwired to the desired logic 0 and logic 1  values at the circuit board level. (These pins can be driven from some other  logic that allows the programming mode to be modified, but this is rarely done  in practice.)

In addition to the hard-wired mode pins, an additional pin is used to instruct  the FPGA to actually commence the configuration, while yet another pin is  used by the device to report back when it’s finished (there are also ways to  determine if an error occurred during the process). This means that in addition  to configuring the FPGA when the system is first powered up, the device may  also be reinitialized using the original configuration data, if such an occurrence  is deemed necessary.

The configuration port also makes use of additional pins to control the loading  of the data and to input the data itself. The number of these pins depends on the  configuration mode selected, as discussed below. The important point here is that  once the configuration has been completed, most of these pins can subsequently  be used as general-purpose I/O pins (we will return to this point a little later).

Serial Load with FPGA as Master

This is perhaps the simplest programming mode. In the early days, it involved  the use of an external PROM. This was subsequently superceded by an EPROM,  then an E 2  PROM, and now—most commonly—a FLASH-based device. This  special-purpose memory component has a single data output pin that is connected to a configuration data in pin on the FPGA ( Figure 3-4 ).

The FPGA also uses several bits to control the external memory device,  such as a reset signal to inform it when the FPGA is ready to start reading data  and a clock signal to clock the data out.

The idea with this mode is that the FPGA doesn’t need to supply the external memory device with a series of addresses. Instead, it simply pulses the  reset signal to indicate that it wishes to start reading data from the beginning,  and then it sends a series of clock pulses to clock the configuration data out of  the memory device.

The configuration data out signal coming from the FPGA need only be  connected if it is required to read the configuration data from the device for  any reason. One such scenario occurs when there are multiple FPGAs on the  circuit board. In this case, each could have its own dedicated external memory  device and be configured in isolation, as shown in Figure 3-4 . Alternatively,  the FPGAs could be cascaded (daisy-chained) together and share a single  external memory ( Figure 3-5 ).

In this scenario, the first FPGA in the chain (the one connected directly  to the external memory) would be configured to use the serial master mode,  while the others would be serial slaves, as discussed later in this chapter.

Parallel Load with FPGA as Master

In many respects, this is very similar to the previous mode, except that the data  is read in 8-bit chunks from a memory device with eight output pins. Groups of  eight bits are very common and are referred to as bytes. In addition to providing control signals, the original FPGAs supplied the external memory device  with an address that was used to point to whichever byte of configuration data  was to be loaded next ( Figure 3-6 ).

The way this worked was that the FPGA had an internal counter that was  used to generate the address for the external memory. (The original FPGAs  had 24-bit counters, which allowed them to address 16 million bytes of data.)  At the beginning of the configuration sequence, this counter would be initialized with zero. After the byte of data pointed to by the counter had been read,  the counter would be incremented to point to the next byte of data. This process would continue until all of the configuration data had been loaded.

Special-purpose memory devices created for use with FPGAs are now relatively inexpensive (and being FLASH-based, they are also reusable). Thus,  modern FPGAs now use a new variation on this parallel-loading technique. In  this case, the external memory is a special-purpose device that doesn’t require  an external address, which means that the FPGA no longer requires an internal  counter for this purpose ( Figure 3-7 ).

As for the serial mode discussed earlier, the FPGA simply pulses the external memory device’s reset signal to indicate that it wishes to start reading data  from the beginning, and then it sends a series of clock pulses to clock the configuration data out of the memory device.

Parallel Load with FPGA as Slave

The modes discussed above, in which the FPGA is the master, are attractive  because of their inherent simplicity and because they only require the FPGA  itself, along with a single external memory device.

However, a large number of circuit boards also include a microprocessor,  which is typically already used to perform a wide variety of housekeeping  tasks. In this case, the design engineers might decide to use the microprocessor  to load the FPGA ( Figure 3-8 ).

The idea here is that the microprocessor is in control. The microprocessor  informs the FPGA when it wishes to commence the configuration process. It  then reads a byte of data from the appropriate memory device (or peripheral,  or whatever), writes that data into the FPGA, reads the next byte of data from  the memory device, writes that byte into the FPGA, and so on until the configuration is complete.

This scenario conveys a number of advantages, not the least being that the  microprocessor might be used to query the environment in which its surrounding system resides and to then select the configuration data to be loaded into  the FPGA accordingly.

Serial Load with FPGA as Slave

This mode is almost identical to its parallel counterpart, except that only a single bit is used to load data into the FPGA (the microprocessor still reads data out of the memory device one byte at a time, but it then converts this data into  a series of bits to be written to the FPGA).

—Technology Trade-offs—  

● The main advantage of this approach is that it uses fewer I/O pins on the  FPGA. This means that—following the configuration process—only a single I/O pin has the additional track required to connect it to the microprocessor’s data bus.