FONT SIZE : AAA
Whenavalueneedstobestaticthroughoutasimulation,thetypeofelementtouseisaconstant. This is often used to initialize parameters or to set fixed register values for comparison. A constant can be declared for any defined type in VHDL with examples as follows:
1 constant a : integer := 1;
2 constant b : real := 0.123;
3 constant c : std_logic := 0;
Signals are the link between processes and sequential elements within processes. They are effectively wires in the design and connect all the design elements together. When simulating signals, the simulator will in turn look at updating the signal values and also checking the sensitivity lists in processes to see whether any changes have occurred that will mean that processes become active.
Signals can be assigned immediately or with a time delay, so that an event is scheduled for sometime in the future (after the specified delay). It is also important to recognize that signals are not the same as a set of sequential program code (such as in C), but are effectively concurrent signals that will not be able to be considered stable until the next time the process is activated.
Examples of signal declaration and assignment are shown below:
1 signal sig1 : integer := 0;
2 signal sig2 : integer := 1;
3 sig1 <= 14;
4 sig1 <= sig2;
5 sig1 <= sig2 after 10 ns;
While signals are the external connections between processes, variables are the internal values within a process. They are only used in a sequential manner, unlike the concurrent nature of signals within and between processes. Variables are used within processes and are declared and used as follows:
1 variable var1 : integer := 0;
2 variable var2 : integer := 1;
3 var1 := var2;
Notice that there is no concept of a delay in the variable assignment; if you need to schedule an event, it is necessary to use a signal.
VHDL has a set of standard Boolean operators built in, which are self explanatory. The list of operators are and, or, nand, not, nor, xor. These operators can be applied to BIT, BOOLEAN, or logic types with examples as follows:
1 out1 <= in1 and in2;
2 out2 <= in3 or in4;
3 out5 <= not in5;
There are a set of arithmetic operators built into VHDL which again are self explanatory and these are described and examples provided as follows:
| Operator | Description | Example |
+ | Addition | out1 <= in1 + in2; |
VHDL has a set of standard comparison operators built in, which are self explanatory. The operators are =, / =, <, <=, >, >=. These operators can be applied to a variety of types as follows:
1 in1 < 1
2 in1 /= in2
3 in2 >= 0.4
VHDL has a set of six built-in logical shift functions which are summarized in the following table:
| Operator | Description | Example |
sll srl sla sra rol ror | Shift Left Logical Shift Left Arithmetic Shift Right Arithmetic Rotate Left Rotate Right | reg <= reg sll 2; reg <= reg srl 2; reg <= reg sla 2; reg <= reg sra 2; |
The concatenation function in VHDL is denoted by the & symbol and is used as follows:
1 A <= 1111;
2 B <= 000
3 out1 <= A & B & 1; −− out1 = 11110001;
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories: EEPROM
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Obsolete -
RoHS: No RoHS
Support
