Adding a Further Interrupt Source

In this exercise we will add an additional source of interrupt to the project created in Exercise 2B in the form of an AXI Timer.

(a) Launch Vivado by double-clicking on the Vivado desktop icon: , or by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1 > Vivado 2014.1 

(b) When the program launches, open the previously created project by selecting Open Project. The previously created project should appear in the list of recent projects as C:/Zynq_Book/ zynq_interrupts/zynq_interrupts.xpr so click on it. If it doesn’t, click Browse Projects. and navigate to that directory, selecting zynq_interrupts.xpr and clicking open. 

(c) Open the block design from the sources panel by expanding the sources and double clicking on the block design as highlighted in Figure 2.25.

(d) With the block diagram now open we will add an AXI Timer to the design. In the Vivado IP Integrator Diagram canvas, right-click anywhere and select Add IP. Enter timer in the search field and add the IP AXI TIMER to the design by either dragging it onto the canvas or selecting it and pressing ENTER.

(e) Select Run Connection Automation option from the Designer Assistance message at the top of the Diagram window and select/axi_timer_0/S_AXI and click OK to connect the timer to the AXI Interconnect.

(f) Note that in Figure 2.27 the AXI Timer features an interrupt request, which requires connection to the Zynq PS. However, we already have an interrupt connected to the input of the PS. This input is a shared interrupt port, and so accepts multiple interrupts via one signal. We therefore require an additional IP block to concatenate these two interrupt requests into one signal. In the canvas, right-click anywhere and select Add IP. Enter concat in the search field and add the IP Concat to the design.

(g) Remove the connection to IRQ_F2P[0:0] on the Zynq PS by clicking it and pressing DELETE. Connect the output from the Concat block, xlconcat_0 to this instead. Then, connect the interrupt request from the GPIO to In0[0:0] and the interrupt from the timer to In1[0:0], creating a shared interrupt signal that is passed to the PS. Your block diagram should be similar to Figure 2.29.

We now need to regenerate the output products, update the HDL wrapped and generate a new bitstream for our altered design.

(h) Right-click on the top-level system design and select Create HDL Wrapper. selecting the default option as previous. Click OK. 

(i) In Flow Navigator, click Generate Bitstream from the Program and Debug section. If a dialogue window appears prompting you to save your design, click Save. 

(j) A dialogue window will open requesting that you launch synthesis and implementation before starting the Generate Bitstream process. Click Yes to accept. Again these back-to-back processes may take a few minutes, depending on the power of your computer system. 

(k) When this process is completed click OK. 

(l) Select File > Export > Export Hardware for SDK. from the Menu Bar. 

(m) The Export Hardware for SDK dialogue window will open. Ensure that the options to Include bitstream and Launch SDK are selected, and Click OK. A dialog will be presented asking if you wish to overwrite an exported file, which is the initial system featuring a single interrupt. Select Yes for this and any further prompts. 

(n) Once the SDK opens and builds the project, we will alter our application to make use of the new interrupt source. Right-click on the project interrupt_counter in the Project Explorer and select Delete.

Repeat for the BSP, interrupt_controller_bsp.  

Repeat the steps outlined in Exercise 2B (a) to (h) for creating a new application project, BSP and importing a source file, this time selecting interrupt_counter_tut_2D.c.

Notice the inclusion of a second interrupt handler, TMR_Intr_Handler(void *data); which will increment the value of the counter after the timer has expired three times, writing the new value to the LEDs.

Additional code has been included in the main to configure and start the timer, and full details of these functions can be found in the system.mms. The function IntcInitFunction(u16 DeviceId, XTmrCtr *TmrInstancePtr,XGpio *GpioInstancePtr); also contains additional code to connect the timer interrupt to the handler and enable it.

In brief, the timer is loaded with a value TMR_LOAD and configured to automatically reload on each expiration. The interrupt handler keeps track of the number of expirations and after three expirations performs the required steps, otherwise it simply increments the variable storing the number of expirations.

Save the file.

(o) Download the bitstream to the Zynq PL by selecting Xilinx Tools > Program FPGA from the Menu bar. (p) Once the blue LED signalling successful programming lights, select zynq_interrupts in Project Explorer. Right-click and select Run As > Launch on Hardware. Note that the counter will increment by 1 every time the timer expires three times. The buttons still operate as in the previous exercise. This completes this tutorial and systems utilising both a single and multiple interrupt sources have been created and tested.