FONT SIZE : AAA
For the remainder of this chapter we shall consider only SRAM-based FPGAs. Remember that these devices are volatile, which means they have to be programmed in-system (on the circuit board), and they always need to be reprogrammed when power is first applied to the system.
From the outside world, we can visualize all of the SRAM configuration cells as comprising a single (long) shift register. Consider a simple bird’s-eye view of the surface of the chip showing only the I/O pins/pads and the SRAM configuration cells ( Figure 3-3 ).
As a starting point, we shall assume that the beginning and end of this register chain are directly accessible from the outside world. However, it’s important to note that this is only the case when using the configuration port programming mechanism in conjunction with the serial load with FPGA as master or serial load with FPGA as slave programming modes, as discussed below.
Also note that the configuration data out pin/signal shown in Figure 3-3 is only used if multiple FPGAs are to be configured by cascading (daisy- chaining) them together or if it is required to be able to read the configuration data back out of the device for any reason.
In the case of FPGAs containing large blocks of embedded (block) RAM, the cores of these blocks are implemented out of SRAM latches, and each of these latches is a configuration cell that forms a part of our “ imaginary ” register chain.
One interesting point is that each 4-input LUT (see Figure 3-2 ) can be configured to act as a LUT, as a small (16 1) chunk of distributed RAM, or as a 16-bit shift register. All of these manifestations employ the same group of 16 SRAM latches, where each of these latches is a configuration cell that forms a part of our imaginary register chain.
How is the 16-bit shift register implemented?
A trick circuit is employed using the concept of a capacitive latch that prevents classic race conditions (this is pretty much the same way designers built flip-flops out of discrete transistors, resistors, and capacitors in the early 1960s).
Figure 3-3 shows the configuration cells presented as a single programming chain. As there can be tens of millions of configuration cells, this chain can be very long indeed. Some FPGAs are architected so that the configuration port actually drives a number of smaller chains. This allows individual portions of the device to be configured and facilitates a variety of concepts such as modular and incremental design.
As was previously noted, the register in the programmable logic block has an associated configuration cell that specifies whether it is to be initialized with a logic 0 or a logic 1. Each FPGA family typically provides some mechanism such as an initialization pin that, when placed in its active state, causes all of these registers to be returned to their initialization values (this mechanism does not reinitialize any embedded [block] or distributed RAMs).
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories:
Lifecycle:Active Active
RoHS: -
Manufacturer:Xilinx
Product Categories: Memory - Configuration Proms for FPGA's
Lifecycle:Active Active
RoHS: -
Support
