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The process in VHDL is the mechanism by which sequential statements can be executed in the correct sequence, and with more than one process, concurrently. Each process consists of a sensitivity list, declarations, and statements. The basic process syntax is given below:
1 process sensitivity_list is
2 −− declaration part
3 begin
4 −− statement part
5 end process;
The sensitivity list allows a process to be activated when a specific signal changes value; for example a typical usage would be to have a global clock and reset signal to control the activity of the process, as follows:
1 process (clk, rst) is
2 begin
3 −− process statements
4 end process;
In this example, the process would only be activated when either clk or rst changed value. Another way of encapsulating the same behavior is to use a wait statement in the process so that the process is automatically activated once, and then waits for activity on either signal before running the process again. The same process could then be written as follows:
1 process
2 begin
3 −− process statements
4 wait on clk, rst;
5 end process;
In fact, the location of the wait statement is not important, as the VHDL simulation cycle executes each process once during initialization, and so the wait statement could be at the start or the end of the process and the behavior would be the same in both cases.
In the declaration section of the process, signals and variables can be defined locally as described previously; for example, a typical process may look like the following:
1 process (a) is
2 signal na : bit;
3 begin
4 na <= not a;
5 end process;
The local signal na and the process are activated by changes on the signal a which is externally declared (with respect to the process).
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