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The underlying concept associated with programming an FPGA is relatively simple (i.e., load the configuration file into the device). It can, however, be a little tricky to wrap one’s brain around all of the different facets associated with this process, so we’ll start with the basics and work our way up. Initially, let’s assume we have a rudimentary device consisting only of an array of very simple programmable logic blocks surrounded by programmable interconnect ( Figure 3-1 ).
Any facets of the device that may be programmed are done so by means of special configuration cells. The majority of FPGAs are based on the use of SRAM cells, but some employ FLASH (or E 2 ) cells, while others use antifuses.
Irrespective of the underlying technology, the device’s interconnect has a large number of associated cells that can be used to configure it so as to connect the device’s primary inputs and outputs to the programmable logic blocks and these logic blocks to each other. (In the case of the device’s primary I/Os, which are not shown in Figure 3-1 , each has a number of associated cells that can be used to configure them to accommodate specific I/O interface standards and so forth.)
For the purpose of this portion of our discussions, we shall assume that each programmable logic block comprises only a 4-input LUT, a multiplexer, and a register ( Figure 3-2 ). The multiplexer requires an associated c onfiguration cell to specify which input is to be selected. The register requires associated cells to specify whether it is to act as an edge-triggered flip-flop (as shown in Figure 3-2 ) or a level-sensitive latch, whether it is to be triggered by a positive- or negative-going clock edge (in the case of the flip-flop option) or an active-low or active-high enable (if the register is instructed to act as a latch), and whether it is to be initialized with a logic 0 or a logic 1. Meanwhile, the 4-input LUT is itself based on 16 configuration cells.
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Product Categories: Memory - Configuration Proms for FPGA's
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