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While the entity describes the interface and parameter aspects of the model, the architecture defines the behavior. There are several types of VHDL architecture and VHDL allows different architectures to be defined for the same entity. This is ideal for developing behavioral, RTL, and gate level architectures that can be incorporated into designs and tested using the same test benches.
The basic approach for declaring an architecture could be as follows:
1 architecture behavior of test is
2 −− architecture declarations
3 begin
4 −− architecture contents
5 end architecture behavior;
or
1 architecture behavior of test is
2 −− architecture declarations
3 begin
4 −− architecture contents
5 end behavior;
After the declaration of the architecture name and before the begin statement, any local signals or variables can be declared. For example, if there were two internal signals to the architecture called sig1 and sig2, they could be declared in the declaration section of the model as follows:
1 architecture behavior of test is
2 signal sig1, sig2 : bit;
3 begin
Then the signals can be used in the architecture statement section.
VHDL architectures can have a variety of structures to achieve different types of functionality. Simple combinatorial expressions use signal assignments to set new signal values as shown below:
1 out1 <= in1 and in2 after 10 ns;
Note that for practical design, the use of the after 10ns statement is not synthesizable. In practice, the only way to ensure correct synthesizable design is to either make the design delay insensitive or synchronous. The design of combinatorial VHDL will result in additional delays due to the technology library gate delays, potentially resulting in glitches or hazards. An example of a multiple gate combinatorial architecture, using internal signal declarations is given below:
1 architecture behavioral of test is
2 signal int1, int2 : bit;
3 begin
4 int1 <= in1 and in2;
5 int2 <= in3 or in4;
6 out1 <= int1 xor int2;
7 end architecture behavioral;
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