Creating a Zynq System with Interrupts in Vivado

In this exercise we will create a simple Zynq embedded system which implements two General Purpose Input/Output (GPIO) controllers in the PL of the Zynq device on the ZedBoard, one of which uses the push buttons to generate interrupts. The other GPIO controller will connect to the LEDs. Both will also be connected to the Zynq processor via an AXI bus connection, allowing the LEDs to be controlled by a software application which we will create in Exercise 2C.

(a) In the Flow Navigator window, select Create Block Design from the IP Integrator section, as in Figure 2.4:

The Create Block Design dialogue will open.

(b) Enter zynq_interrupt_system in the Design name box, as in Figure 2.5:

Click OK. The Vivado IP Integrator Diagram canvas will open in the Workspace.

The first block that we will add to our design will be a Zynq Processing System.

Exercise 2B: Creating a Zynq System with Interrupts in Vivado

(c) In the Vivado IP Integrator Diagram canvas, right-click anywhere and select Add IP, as in Figure 2.6.

Alternatively, select the Add IP option from the information message at the top of the canvas, shown in Figure 2.7.

The pop-up IP Catalog window will open, as in Figure 2.8.

(d) Enter zynq in the search field and select the ZYNQ7 Processing System, ensuring that you select the option for Version 5.4, as shown in Figure 2.9, and press the Enter key on your keyboard.

As in the previous tutorial, the next step is to connect the DDR and FIXED_IO interface ports on the Zynq PS to the top-level interface ports on the design.

(e) Select the Run Block Automation option from the Designer Assistance message at the top of the Diagram window. Select OK, ensuring that the option to Apply Board Preset is selected, to generate the external connections for both the DDR and FIXED_IO interfaces, and apply the relevant board presets.

Your block diagram should now resemble Figure 2.10.

Now that the main Zynq PS has been added to our design and configured, we can now add further blocks which will be placed in the PL to add functionality to the system. In this case we require an AXI GPIO block for the LEDs and another for the push buttons.

(f) Right-click in an empty area of the Diagram window and select Add IP. Enter GPIO in the search field and add an instance of the AXI GPIO IP. Repeat this procedure to add a second AXI GPIO block to the design.

We will now use the IP Integrator Designer Assistance tool to automate the connection of the AXI GPIO blocks to the ZYNQ7 Processing System.

(g) Click Run Connection Automation from the Designer Assistance message at the top of the Diagram window and select /axi_gpio_0/S_AXI, as shown Figure 2.11.

Click OK to ensure automatic clock connection, which adds the Processor System Reset Module and the AXI Interconnect blocks.

(h) Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO.  The Run Connection Automation dialogue will open, as in Figure 2.12. Select btns_5bits from the drop-down menu, and click OK.

(i) Repeat steps (g) and (h) for the second GPIO block, this time selecting leds_8bits for / axi_gpio_1/GPIO.

You will now have a system that is similar to Figure 2.13. We now need to configure the system to utilise hardware interrupts from the push buttons to trigger functions in the Zynq PS.

(j) Double--click on the GPIO block connected to the push buttons, axi_gpio_0, to open the Recustomize IP window,.

Click the IP Configuration tab and enable interrupts from the push buttons by clicking in the box highlighted in Figure 2.14 and click OK. This will add an additional output port for the interrupt request to the GPIO block as in Figure 2.15.

Now we must configure the Zynq PS to accept interrupt requests.

(k) Double-click on the Zynq PS block, processing_system7_0, to open the Re-Customize IP window.

(l) Select Interrupts from the Page Navigator on the left-hand side and expand the menu on the right as in Figure 2.16. Since we want to allow interrupts from the programmable logic to the processing system, tick the box to enable Fabric Interrupts, then click to enable the shared interrupt port as in Figure 2.16. This means interrupts from the PL can be connected to the interrupt controller within the Zynq PS. Click OK.

(m) Make a connection between the interrupt request of the GPIO block and the newly created interrupt port of the Zynq PS, highlighted in Figure 2.17.

Your final design should resemble Figure 2.18, although the positioning of your blocks may be different.

(n) Save your design by selecting File > Save Block Design from the Menu Bar. 

(o) Validate the design by selecting Tools > Validate Design from the Menu Bar. This will run a Design-Rule-Check (DRC).  Alternatively, select the Validate Design button, , from the Main Toolbar. 

(p) A Validate Design dialogue should appear to confirm that validation of the design was successful. Click OK, to dismiss the message.

With the design successfully validated, we can now move on to generating the HDL design files for the system. The procedure here is identical to the previous tutorial, First Designs on Zynq.

(q) In the Sources window of the Data Windows pane, select the Sources tab. 

(r) Right-click on the top-level system design, which in this case is zynq_interrupt_system, and select Create HDL Wrapper. 

The Create HDL Wrapper dialogue window will open. Accept the default option specifying that VIvado should manage the wrapper and click OK.

With all HDL design files generated, the next step in Vivado is to implement our design and generate a bitstream file.

(s) In Flow Navigator, click Generate Bitstream from the Program and Debug section.

If a dialogue window appears prompting you to save your design, click Save. The combination of running the synthesis, implementation and bitstream generation processes back-to-back may take a few minutes, depending on the power of your computer system.

(t) Once the bitstream generation is complete a dialogue window will open to inform you that the process has been completed successfully, as in Figure 2.19.

Select Open Implemented Design, and click OK.

At this point you will be presented with the Device view, where you can see the PL resources which are utilised by the design.

With the bitstream generation complete, the final step in Vivado is to export the design to the SDK, where we will create the software application that will allow the Zynq PS to control the LEDs on the ZedBoard.

(u) Select File > Export > Export Hardware for SDK. from the Menu Bar. 

(v) The Export Hardware for SDK dialogue window will open. Ensure that the options to Include bitstream and Launch SDK are selected, and Click OK.

This concludes the steps that are required in Vivado IDE. All hardware components of the system have been configured and generated. In the next exercise we will create the software application that utilises this hardware system.