GENERAL-PURPOSE I/O

Today’s FPGA packages can have a thousand or more pins, which are arranged as an array across the base of the package. Similarly, when it comes to the silicon chip inside the package, flip-chip packaging strategies allow the power, ground, clock, and I/O pins to be presented across the surface of the chip. Purely for the purposes of these discussions (and illustrations), however, it makes things simpler if we assume that all of the connections to the chip are presented in a ring around the circumference of the device, as indeed they were for many years.

Confifi gurable I/O Standards

Let’s consider for a moment an electronic product from the perspective of the architects and engineers designing the circuit board. Depending on what they are trying to do, the devices they are using, the environment the board will operate in, and so on, these designers will select a particular standard to be used to transfer data signals. (In this context, “ standard ” refers to electrical aspects of the signals, such as their logic 0 and logic 1 voltage levels.) The problem is that there is a wide variety of such standards, and it would be painful to have to create special FPGAs to accommodate each variation. For this reason, an FPGA’s general-purpose I/O can be configured to accept and generate signals conforming to whichever standard is required. These generalp urpose I/O signals will be split into a number of banks—we’ll assume eight such banks numbered from 0 to 7 ( Figure 2-22 ). The interesting point is that each bank can be configured individually to support a particular I/O standard. Thus, in addition to allowing the FPGA to work with devices using multiple I/O standards, this allows the FPGA to actually be used to interface between different I/O standards (and to translate between different protocols that may be based on particular electrical standards).

Bird’s eye view of chip showing general purpose IO bankspng

Confifi gurable I/O Impedances

The signals used to connect devices on today’s circuit board often have fast edge rates (this refers to the time it takes the signal to switch between one logic value and another). In order to prevent signals reflecting back (bouncing around), it is necessary to apply appropriate terminating resistors to the FPGA’s input or output pins. In the past, these resistors were applied as discrete components that were attached to the circuit board outside the FPGA. However, this technique became increasingly problematic as the number of pins started to increase and their pitch (the distance between them) shrank. For this reason, today’s FPGAs allow the use of internal terminating resistors whose values can be configured by the user to accommodate different circuit board environments and I/O standards.

Core versus I/O Supply Voltages

TABLE 2-1 Supply Voltages versus Technology Nodes
Year	Supply (Core Voltage (V))	Technology Node (nm)
1998	3.3	350
1999	2.5	250
2000	1.8	180
2001	1.5	150
2003	1.2	130

The supply voltage (which is actually provided using large numbers of power and ground pins) is used to power the FPGA’s internal logic. For this reason, this is known as the core voltage . However, different I/O standards may use signals with voltage levels significantly different from the core voltage, so each bank of general-purpose I/Os can have its own additional supply pins.

Insider Info

It’s interesting to note that—from the 350 nm node onward—the core voltage has scaled fairly linearly with the process technology. However, there are physical reasons not to go much below 1 V (these reasons are based on technology aspects such as transistor input switching thresholds and voltage drops), so this “ voltage staircase ” might start to tail off in the not-so-distant future.

TABLE OF CONTENTS

Confifi gurable I/O Standards

Confifi gurable I/O Impedances

Core versus I/O Supply Voltages

Insider Info