CLOCK MANAGERS

All of the synchronous elements inside an FPGA—for example, the registers  configured to act as flip-flops inside the programmable logic blocks—need to  be driven by a clock signal. Such a clock signal typically originates in the outside world, comes into the FPGA via a special clock input pin, and is then  routed through the device and connected to the appropriate registers.

Clock Trees

Consider a simplified representation that omits the programmable logic  blocks and shows only the clock tree and the registers to which it is connected  ( Figure 2-15 ).

This is called a clock tree because the main clock signal branches again  and again (the flip-flops can be considered the “ leaves ” on the end of the  branches). This structure is used to ensure that all of the flip-flops see their  versions of the clock signal as close together as possible. If the clock were  distributed as a single long track driving all of the flip-flops one after another,  then the flip-flop closest to the clock pin would see the clock signal much  sooner than the one at the end of the chain. This is referred to as skew, and it can cause all sorts of problems (even when using a clock tree, there will be  a certain amount of skew between the registers on a branch and between  branches). The clock tree is implemented using special tracks and is separate  from the general-purpose programmable interconnect. The scenario shown  above is actually very simplistic.

Clock Managers

Instead of configuring a clock pin to connect directly into an internal clock  tree, that pin can be used to drive a special hard-wired function (block) called  a clock manager that generates a number of daughter clocks ( Figure 2-16 ).

These daughter clocks may be used to drive internal clock trees or external  output pins that can be used to provide clocking services to other devices on  the host circuit board. Each family of FPGAs has its own type of clock manager (there may be multiple clock manager blocks in a device), where different  clock managers may support only a subset of the following features:

Jitter removal : For the purposes of a simple example, assume that the clock  signal has a frequency of 1 MHz (in reality, of course, this could be much, much  higher). In an ideal environment each clock edge from the outside world would  arrive exactly 1 millionth of a second after its predecessor. In the real world,  however, clock edges may arrive a little early or a little late. As one way to visualize this effect—known as jitter —imagine if we were to superimpose multiple  edges on top of each other; the result would be a “ fuzzy ” clock ( Figure 2-17 ).  The FPGA’s clock manager can be used to detect and correct for this jitter and to  provide “ clean ” daughter clock signals for use inside the device ( Figure 2-18 ).

Frequency synthesis : It may be that the frequency of the clock signal being  presented to the FPGA from the outside world is not exactly what the design  engineers wish for. In this case, the clock manager can be used to generate  daughter clocks with frequencies that are derived by multiplying or dividing  the original signal. As a really simple example, consider three daughter clock  signals: the first with a frequency equal to that of the original clock, the second  multiplied to be twice that of the original clock, and the third divided to be half that of the original clock ( Figure 2-19 ). Once again, Figure 2-19 reflects  very simple examples. In the real world, one can synthesize all sorts of internal  clocks, such as an output that is four-fifths the frequency of the original clock.

Phase shifting : Certain designs require the use of clocks that are phase  shifted (delayed) with respect to each other. Some clock managers allow you  to select from fixed phase shifts of common values such as 120° and 240° (for  a three-phase clocking scheme) or 90°, 180°, and 270° (if a four-phase clocking scheme is required). Others allow you to configure the exact amount of  phase shift you require for each daughter clock. For example, let’s assume that  we are deriving four internal clocks from a master clock, where the first is in phase with the original clock, the second is phase shifted by 90°, the third by  180°, and so forth ( Figure 2-20 ).

Auto-skew correction : For the sake of simplicity, let’s assume that we’re  talking about a daughter clock that has been configured to have the same frequency and phase as the main clock signal coming into the FPGA. By default,  however, the clock manager will add some element of delay to the signal as  it performs its machinations. Also, more significant delays will be added by  the driving gates and interconnect employed in the clock’s distribution. The  result is that—if nothing is done to correct it—the daughter clock will lag  behind the input clock by some amount. Once again, the difference between  the two signals is known as skew . Depending on how the main clock and the  daughter clock are used in the FPGA (and on the rest of the circuit board), this  can cause a variety of problems. Thus, the clock manager may allow a special  input to feed the daughter clock. In this case, the clock manager will compare  the two signals and specifically add additional delay to the daughter clock sufficient to realign it with the main clock ( Figure 2-21 ). To be a tad more specific, only the prime (zero phase-shifted) daughter  clock will be treated in this way, and all of the other daughter clocks will be phase aligned to this prime daughter clock.

—Technology Trade-offs—

● Some FPGA clock managers are based on phase-locked loops (PLLs),  while others are based on digital delay-locked loops (DLLs). PLLs have  been used since the 1940s in analog implementations, but recent emphasis  on digital methods has made it desirable to match signal phases digitally.  PLLs can be implemented using either analog or digital techniques, while  DLLs are by definition digital in nature. 

● The proponents of DLLs say that they offer advantages in terms of precision,  stability, power management, noise insensitivity, and jitter performance.