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Home > FPGA Technical Tutorials > The Zynq Book Tutorials > Next Steps in Zynq SoC Design > Expanding the Basic IP Integrator Design

Expanding the Basic IP Integrator Design

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In this exercise we will expand upon the previous project in Vivado IDE by adding additional GPIO and configuring the system to utilise interrupts. For the sake of clarity and understanding, we will run through the building of a basic system once more. Start by launching the Vivado IDE.

(a) Launch Vivado by double-clicking on the Vivado desktop icon: , or by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1 > Vivado 2014.1

(b) When Vivado loads, you will be presented with the Getting Started screen as in Figure 2.1.

Vivado IDE Getting Started screen -.png

(c) Select the option to Create New Project as in Figure 2.2

New Project dialogue -.png


Click Next.

(d) At the Project Name dialogue, enter zynq_interrupts as the Project name and C:/Zynq_Book as Project location.

Make sure that you select the option to Create project subdirectory. All options should be the same as shown below:

image.png

Click Next.

A directory named Zynq_Book will be created on your C drive if it did not already exist.

(e) At the Project Type dialogue, select RTL Project and ensure that the option Do not specify sources at this time is not selected:

image.png

Click Next.

(f) Select VHDL as the Target language in the Add Sources dialogue.

If existing sources, in the form of HDL or netlist files, were to be added to the project they could be imported at this stage.

As we do not have any sources to add to the project, click Next.

(g) The Add Existing IP (optional) dialogue will open. If existing IP sources were to be included in the project, they could be added here. As we do not have any existing IP to add, click Next

(h) The Add Constraints (optional) dialogue will open. This is the stage where any physical or timing constraints files could be added to the project.  As we do not have any constraints files to add, click Next

(i) From the Default Part dialogue, select Boards from the Specify box and choose ZedBoard Zynq Evaluation and Development Kit, Board Version c from the list of boards, as shown in Figure 2.3.

Default part dialogue options -.png

Click Next.

(j) In the New Project Summary dialogue, review the specified options, and click Finish to create the project.

As in the previous tutorial we will now create the basic Zynq embedded system design before adding and configuring additional IP to utilise hardware interrupts.










  • XC4VLX60-11FF668C

    Manufacturer:Xilinx

  • FPGA Virtex-4 LX Family 59904 Cells 90nm Technology 1.2V 668-Pin FCBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

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  • XC4VLX60-11FFG668I

    Manufacturer:Xilinx

  • FPGA Virtex-4 LX Family 59904 Cells 90nm Technology 1.2V 668-Pin FCBGA
  • Product Categories: FPGAs (Field Programmable Gate Array)

    Lifecycle:Active Active

    RoHS:

  • XC4VLX60-12FFG668C

    Manufacturer:Xilinx

  • FPGA Virtex-4 LX Family 59904 Cells 90nm Technology 1.2V 668-Pin FCBGA
  • Product Categories: FPGAs (Field Programmable Gate Array)

    Lifecycle:Active Active

    RoHS:

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    Manufacturer:Xilinx

  • IC PROM SER C-TEMP 3.3V 44-PLCC
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    Lifecycle:Active Active

    RoHS: -

  • XC18V04-VQ44BRT

    Manufacturer:Xilinx

  • Xilinx QFP44
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    Lifecycle:Active Active

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