Creating a Zynq System in Vivado

In this exercise we will be create a simple Zynq embedded system which implements a General Purpose Input/Output (GPIO) controller in the PL of the Zynq device on the ZedBoard. The GPIO controller will connect to the LEDs. It will also be connected to the Zynq processor via an AXI bus connection, allowing the LEDs to be controlled by a software application which we will create in Exercise 1C.

A graphical representation of the Zynq embedded design is provided in Figure 1.6.

We will begin by creating a new Block Design in Vivado IDE.

(a) In the Flow Navigator window, select Create Block Design from the IP Integrator section, as in Figure 1.7:

The Create Block Design dialogue will open.

(b) Enter first_zynq_system in the Design name box, as in Figure 1.8:

Click OK. The Vivado IP Integrator Diagram canvas will open in the Workspace.

The first block that we will add to our design will be a Zynq Processing System.

(c) In the Vivado IP Integrator Diagram canvas, right-click anywhere and select Add IP, as in Figure 1.9.

Alternatively, select the Add IP option from the information message at the top of the canvas, shown in Figure 1.10.

The pop-up IP Catalog window will open, as in Figure 1.11.

(d) Enter zynq in the search field and select the ZYNQ7 Processing System, as shown in Figure 1.12, and press the Enter key on your keyboard.

You should see a similar message to the following in the Tcl Console window to confirm that the processing system has indeed been configured correctly:

create_bd_cell ‐type ip ‐vlnv xilinx.com:ip:processing_system7:5.4 processing_system7_0

Messages like this will be displayed in the Tcl Console window for all actions carried out on IP Integrator blocks.

The next step is to connect the DDR and FIXED_IO interface ports on the Zynq PS to the top-level interface ports on the design.

(e) Click the Run Block Automation option from the Designer Assistance message at the top of the Diagram window and select /processing_system7_0, as shown in Figure 1.13.

You should notice that the selected item, in this case the ZYNQ7 Processing System, is highlighted in green.

Select OK, to generate the external connections for both the DDR and FIXED_IO interfaces, ensuring that the option to Apply Board Preset is selected.

Your block diagram should now resemble Figure 1.14.

As we are using the ZedBoard platform, and we specified this when creating the project, Vivado will configure the Zynq processor block accordingly.

Now that the main Zynq PS has been added to our design and configured, we can now add further blocks which will be placed in the PL to add functionality to the system. In this case we will only be adding a single block, AXI GPIO, to allow us to access the LEDs on the ZedBoard.

(f) Right-click in an empty area of the Diagram window and select Add IP. Enter GPIO in the search field and add an instance of the AXI GPIO IP.

We will now use the IP Integrator Designer Assistance tool to automate the connection of the AXI GPIO block to the ZYNQ7 Processing System.

(g) Click Run Connection Automation from the Designer Assistance message at the top of the Diagram window and select /axi_gpio_0/S_AXI, as shown Figure 1.15.

This will automate the process of connecting the GPIO to an AXI port, and will automatically instantiate two further IP blocks:

• Processor System Reset Module - This provides customised resets for an entire processing system, including the peripherals, interconnect and the processor itself. 

• AXI Interconnect - Provides an AXI interconnect for the system, allowing further IP and peripherals in the PL to communicate with the main processing system.

Leave the option for Clock Connection (for unconnected clks) to Auto, and Click OK.

All connections between the blocks should be made automatically.

One final connection is required to connect the AXI GPIO block to the LEDs on the ZedBoard. This can also be completed using Designer Assistance.

(h) Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO.

The Run Connection Automation dialogue will open, as in Figure 1.16.

Select LEDs_8Bits from the drop-down menu, and click OK. 

The gpio interface of the AXI GPIO block will automatically be connected to the LEDs on the ZedBoard

(i) Click the Regenerate Layout button to tidy up the design schematic. Your complete design should resemble Figure 1.17.

The positions of the individual IP blocks in your design may vary slightly from Figure 1.17, but the blocks and their connections should be the same.

IP Integrator will automatically assign a memory map for all IP that is present in the design. We will not be changing the memory map in this tutorial, but for future reference we will take a look at the Address Editor.

(j) Select the Address Editor tab from the top of the Workspace window, as shown in Figure 1.18, and expand the Data group.

You can see that IP Integrator has already assigned a memory map (the mapping of specific sections of memory to the memory-mapped registers of the IP blocks in the PL) to the to the AXI GPIO interface, and that it has a range of 64K.

Now that our system is complete, we must first validate the design before generating the HDL design files.

(k) Save your design by selecting File > Save Block Design from the Menu Bar. 

(l) Validate the design by selecting Tools > Validate Design from the Menu Bar. This will run a Design-Rule-Check (DRC).  Alternatively, select the Validate Design button, , from the Main Toolbar, or right-cick anywhere in the Diagram canvas and select Validate Design. 

(m) A Validate Design dialogue should appear to confirm that validation of the design was successful. Click OK, to dismiss the message.

With the design successfully validated, we can now move on to generating the HDL design files for the system.

(n) Switch to the Sources Tab by selecting Window > Sources from the Menu Bar.

(o) Still in the Sources window, right-click on the top-level system design, which in this case is first_zynq_system, and select Create HDL Wrapper, as shown in Figure 1.19.

The Create HDL Wrapper dialogue window will open. Select Let Vivado manage wrapper and auto-update, and click OK.

This will generate the top level HDL wrapper for our system.

All of the source files for the IP blocks that were used in the IP Integrator block diagram, as well as any relevant constraints files, will be generated during the synthesis process. As we specified VHDL as the target language when creating the project in Exercise 1A, all generated source files will be VHDL.

With all HDL design files generated, the next step in Vivado is to implement our design and generate a bitstream file.

(p) In Flow Navigator, click Generate Bitstream from the Program and Debug section. If a dialogue window appears prompting you to save your design, click Save. 

(q) A dialogue window will open requesting that you launch synthesis and implementation before starting the Generate Bitstream process. Click Yes to accept. The combination of running the synthesis, implementation and bitstream generation processes back-to-back may take a few minutes, depending on the power of your computer system.

(r) Once the bitstream generation is complete a dialogue window will open to inform you that the process has been completed successfully, as in Figure 1.20.

Select Open Implemented Design, and click OK.

At this point you will be presented with the Device view, where you can see the PL resources which are utilised by the design.

With the bitstream generation complete, the building of the hardware image is complete. It must now be exported to a software environment where we will build a software application to control and interact with the custom hardware.

The final step in Vivado is to export the design to the SDK, where we will create the software application that will allow the Zynq PS to control the LEDs on the ZedBoard.

(s) Select File > Export > Export Hardware for SDK. from the Menu Bar.

(t) The Export Hardware for SDK dialogue window will open. Ensure that the options to Include bitstream and Launch SDK are selected, as in Figure 1.21, and click OK.

NOTE: For the option to Include bitstream to be enabled, an implemented design must be active. This is the reason that we opened the implemented design in Step (r).

This concludes the steps that are required in Vivado IDE. All hardware components of the system have been configured and generated. In the next exercise we will move on to creating a simple software component which will control the system.