Creating a First IP Integrator Design

In this exercise we will create a new project in Vivado IDE by moving through the stages of the Vivado IDE New Project Wizard.

We will start by launching the Vivado IDE.

(a) Launch Vivado by double-clicking on the Vivado desktop icon: , or by navigating to Start > All Programs > Xilinx Design Tools > Vivado 2014.1> Vivado 2014.1 

(b) When Vivado loads, you will be presented with the Getting Started screen as in Figure 1.1.

(c) Select the option to Create New Project and the New Project Wizard will open, as in Figure 1.2.

Click Next.

(d) At the Project Name dialogue, enter first_zynq_design as the Project name and C:/ Zynq_Book as Project location.

Make sure that you select the option to Create project subdirectory. All options should be the same as shown below:

Click Next. 

A directory named Zynq_Book will be created on your C drive if it did not already exist.

(e) At the Project Type dialogue, select RTL Project and ensure that the option Do not specify sources at this time is not selected:

(f) Select VHDL as the Target language in the Add Sources dialogue.  

If existing sources, in the form of HDL or netlist files, were to be added to the project they could be imported at this stage.  

As we do not have any sources to add to the project, click Next.

(g) The Add Existing IP (optional) dialogue will open. If existing IP sources were to be included in the project, they could be added here. As we do not have any existing IP to add, click Next. 

(h) The Add Constraints (optional) dialogue will open. This is the stage where any physical or timing constraints files could be added to the project.  As we do not have any constraints files to add, click Next. 

(i) From the Default Part dialogue, select Boards from the Specify box and select ZedBoard Zynq Evaluation and Development Kit from the Display Name list and All from the Board Rev list, as shown in Figure 1.3. Select the appropriate revision for your board (in this case Rev. C has been selected).

Click Next.

(j) In the New Project Summary dialogue, review the specified options, and click Finish to create the project.

Now that we have created our first project in Vivado IDE, we can now move on to creating our first Zynq embedded system design.

Before doing that, the Vivado IDE tool layout should be introduced. The default Vivado IDE environment layout is shown in Figure 1.4 (other layouts can be chosen by selecting different perspectives).

With reference to the numbered labels in Figure 1.4, the main components of the Vivado IDE environment are:

1. Menu Bar - The main access bar gives access to the Vivado IDE commands. 

2. Main Toolbar - The main toolbar provides easy access to the most commonly used Vivado IDE commands. Tooltips that provide information for each command on the toolbar can be accessed by hovering the mouse pointer over the corresponding button, as shown in Figure 1.5.

3. Workspace - The workspace provides a larger area for panels which require a greater screen space and those with a graphical interface, such as:

• Schematic panel 

• Device panel 

• Package panel 

• Text editor panel

4. Project Status Bar - The project status bar displays the status of the currently active design. 

5. Flow Navigator - The Flow Navigator provides easy access to the tools and commands that are necessary to guide your design from start to finish, starting in the Project Manager section with design entry and ending with bitstream generation in the Program and Debug section. Run commands are available in the Simulation, Synthesis and Implementation sections to simulate, synthesise and implement the active design.  

6. Data Windows Pane -The Data Windows pane, by default, displays information that relates to design data and sources, including:

• Properties window - Shows information about selected logic objects or device resources. 

• Netlist window - Provides a hierarchical view of the synthesised or elaborated logic design. 

• Sources window - Shows IP Sources, Hierarchy, Libraries and Compile Order views.

7. Status Bar - The status bar displays a variety of information, including:

• Detailed information regarding menu bar and toolbar commands will be shown in the lower left side of the status bar when the command is accessed. 

• When hovering over an object in the Schematic window with the mouse pointer, the object details appear in the status bar. 

• During constraint and placement creation in the Device and Package windows, validity and constraint type will be shown on the left side of the status bar. Site coordinates and type will be shown in the right side.

• The task progress of a running task will be relocated to the right side of the status bar when the Background button is selected.

8. Results Window Area -The Results Window displays the status and results of commands in a set of windows grouped in the bottom of the Vivado IDE environment. As commands progress, messages are generated and log files and reports are created. The related information is shown here. The default windows are:

• Messages - Displays all messages for the active design. 

• Tcl Console - Tcl commands can be entered here an a history of previous commands and outputs are also available. 

• Reports - Quick access is provided to the reports generated throughout the design flow. 

• Log -Displays the log files generated by the simulation, synthesis and implementation processes. 

• Design Runs -Manages runs for the current project.

Additional windows that can appear in this area as required are: Find Results window, Timing Results window and Package Pins window.

With the layout of the Vivado IDE environment introduced, we can now move on to creating the Zynq system.