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At this early stage, it is useful to set out a basic model for the types of digital systems to be discussed in this book. These will be systems incorporating a processor, memories, and peripherals, along with buses connecting the various elements together. (This represents the hardware system, and here we consider a very simplified architecture — more details will be added in later chapters.) This model of the hardware system is shown in Figure 1.3.
.png "The hardware system architecture of an embedded SoC (simplified).png")
The processor can be regarded as the central element of the hardware system. The software system (a software ‘stack’) is run on the processor, comprising applications (usually based on an Operating System (OS)), and with a lower layer of software functionality for interfacing with the hardware system. Communication between system elements takes place via interconnections. These may be in the style of direct, point-to-point links, or buses serving multiple components. In the latter case, a protocol is required to manage access to the bus. Note that, although a single bus with connected peripherals is shown in Figure 1.3, a processor may serve several connected buses.
Peripherals are functional components residing away from the processor, and in general these perform one of three functions: (i) coprocessors — elements that supplement the primary processor, usually optimised for a certain task; (ii) cores for interacting with external interfaces, e.g. connecting to LEDs and switches, codecs, etc.; and (iii) additional memory elements. Later in the book, we will consider peripherals in more detail, but at this point it is useful to regard them as discrete functional blocks that can be designed, tested and integrated into a system, and also ‘packaged’ for later reuse.
Figure 1.4 provides a view of the hardware system shown in Figure 1.3, mapped to the Zynq device (depicted in Figure 1.2). The architectures of both have been substantially simplified, but the objective at this stage is to provide a high level clarification of how embedded SoCs map to Zynq devices. The PS has a fixed architecture and hosts the processor and system memory, whereas the PL is completely flexible, giving the designer a ‘blank canvas’ to create custom peripherals, or to reuse standard ones. The interconnections are implemented via AXI interfaces linking the PS and PL.
The software system can also be seen on the left hand side of Figure 1.4. Software is hosted on the processor, which here is the ARM Cortex-A9, residing within the Zynq PS. It comprises a hierarchy of software elements, and this aspect will also be expanded upon later in the book.
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