SOME TECHNOLOGY BACKGROUND

The first FPGA devices contained only a few thousand simple logic gates (or the equivalent), and the flows used to design these components—p redominantly based on the use of schematic capture—were easy to understand and use. By comparison, today’s FPGAs are incredibly complex, and there are more design tools, flows, and techniques than you can swing a stick at. In this section we’ll look at some technology basics.

Fusible-link Technology 

Let’s first consider a very simple programmable function with two inputs called a and b and a single output y ( Figure 1-1 ).

The inverting NOT gates associated with the inputs mean that each input is available in both its true (unmodified) and complemented (inverted) form. Observe the locations of the potential links. In the absence of any of these links, all of the inputs to the AND gate are connected via pull-up resistors to a logic 1 value. In turn, this means that the output y will always be driving a logic 1, which makes this circuit a very boring one in its current state. To make this function more interesting, we need a mechanism that allows us to establish one or more of the potential links. This mechanism is fusible-link technology. In this case, the device is manufactured with all of the links in place, with each link referred to as a fuse ( Figure 1-2 ). 

These fuses are similar to the fuses you find in household products like a television. If anything untoward occurs such that the television starts to consume too much power, its fuse will burn out, resulting in an open circuit, which protects the rest of the unit from harm. Of course, the fuses in silicon chips are formed using the same processes that are employed to create the transistors and wires on the chip, so they’re microscopically small.

Although fusible-link technology is not used in today’s FPGAs, it sets the stage for understanding technologies that are, so we’ll explore it briefly. When you purchase a programmable device based on fusible links, all the fuses are initially intact. This means that, in its unprogrammed state, the output from our example function is always logic 0. (Any 0 presented to the input of an AND gate will cause its output to be 0, so if input a is 0, the output from the AND will be 0. Alternatively, if input a is 1, then the output from its NOT gate—which we shall call !a —will be 0, and once again the output from the AND will be 0. A similar situation occurs in the case of input b .)

The point is that design engineers can selectively remove undesired fuses by applying pulses of relatively high voltage and current to the device’s inputs. For example, consider what happens if we remove fuses F af and F bt ( Figure 1-3 ). 

Removing these fuses disconnects the complementary version of input a and the true version of input b from the AND gate (the pull-up resistors associated with these signals cause their associated inputs to the AND to be presented with logic 1 values). This leaves the device to perform its new function, which is y  a & !b . (The “ & ” character in this equation is used to represent the AND, while the “ ! ” character is used to represent the NOT.) This process of removing fuses is typically called programming the device, but it may also be called blowing the fuses or burning the device.

FPGA Programming Technologies 

Three different major technologies are in use today for programming FPGAs: antifuse, SRAM, and FLASH EPROM. 

Antifuse Technology 

 As a diametric alternative to fusible-link technologies, we have their antifuse counterparts, in which each configurable path has an associated link called an antifuse. In its unprogrammed state, an antifuse has such a high resistance that it may be considered an open circuit (a break in the wire).

How It Works 

Figure 1-4 shows how the device appears when first purchased. However, antifuses can be selectively “ grown ”(programmed) by applying pulses of relatively high voltage and current to the device’s inputs. For example, if we add the antifuses associated with the complementary version of input a and the true version of input b, our device will now perform the function y  !a &b ( Figure 1-5 ). An antifuse commences life as a microscopic column of amorphous (noncrystalline) silicon linking two metal tracks. In its unprogrammed state, the amorphous silicon acts as an insulator with a very high resistance in excess of 1 billion ohms ( Figure 1-6a ). The act of programming this particular element effectively “ grows ”a link, known as a via, by converting the insulating amorphous silicon in conducting polysilicon ( Figure 1-6b ).

FIGURE 1-4 Unprogrammed antifuse links.

FIGURE 1-5 Programmed antifuse links.

FIGURE 1-6 Growing an antifuse.

 —Technology Trade-offs—

● Not surprisingly, devices based on antifuse technologies are OTP, because once an antifuse has been grown, it cannot be removed, and there’s no changing your mind.

● Antifuse devices tend to be faster and require lower power. 

SRAM-based Technology 

There are two main versions of semiconductor RAM devices: dynamic RAM (DRAM) and static RAM (SRAM). DRAM technology is of very little interest with regard to programmable logic, so we will focus on SRAM.

The “ static ” qualifier associated with SRAM means that—once a value has been loaded into an SRAM cell—it will remain unchanged unless it is specifically altered or until power is removed from the system.

How It Works 

Consider the symbol for an SRAM-based programmable cell (Figure 1-7). The entire cell comprises a multitransistor SRAM storage element whose output drives an additional control transistor. Depending on the contents of the storage element (logic 0 or logic 1), the control transistor will be either OFF (disabled) or ON (enabled). 

SRAM is currently the dominant FPGA technology

FIGURE 1-7 An SRAM-based programmable cell.

—Technology Trade-offs— 

● A disadvantage of SRAM-based programmable devices is that each cell consumes a significant amount of silicon real estate because the cells are formed from four or six transistors configured as a latch. 

● Another disadvantage is that the device’s configuration data (programmed state) will be lost when power is removed from the system, so these devices always have to be reprogrammed when the system is powered on. 

● Advantages are that such devices can be reprogrammed quickly and easily, and SRAM uses a standard fabrication technology that is always being improved upon.

FLASH-based Technologies 

 A relatively new technology known as FLASH is being used in some FPGAs today. This technology grew out of an earlier technology known as erasable programmable read-only memory (EPROM) that allows devices to be programmed, erased, and reprogrammed with new data. We will first look at how EPROMs work before discussing FLASH. 

An EPROM transistor has the same basic structure as a standard MOS transistor, but with the addition of a second polysilicon floating gate isolated by layers of oxide ( Figure 1-8 ).

FIGURE 1-8 Standard MOS versus EPROM transistors.

How It Works 

In its unprogrammed state, the floating gate is uncharged and doesn’t affect the normal operation of the control gate. In order to program the transistor, a relatively high voltage (on the order of 12V) is applied between the control gate and drain terminals. This causes the transistor to be turned hard on, and energetic electrons force their way through the oxide into the floating gate in a process known as hot (high energy) electron injection. When the programming signal is removed, a negative charge remains on the floating gate. This charge is very stable and will not dissipate for more than a decade under normal operating conditions. The stored charge on the floating gate inhibits the normal operation of the control gate and, thus, distinguishes those cells that have been programmed from those that have not. This means we can use such a transistor to form a memory cell (Figure 1-9). 

FIGURE 1-9 An EPROM transistor-based memory cell.

In its unprogrammed state, as provided by the manufacturer, all of the floating gates in the EPROM transistors are uncharged. In this case, placing a row line in its active state will turn on all of the transistors connected to that row, thereby causing all of the column lines to be pulled down to logic 0 via their respective transistors. In order to program the device, engineers can use the inputs to the device to charge the floating gates associated with selected transistors, thereby disabling those transistors. In these cases, the cells will appear to contain logic 1 values. These devices were initially intended for use as programmable memories, but the same technology was applied to more general-purpose PLDs, which became known as erasable PLDs (EPLDs). The main problems with EPROMs are their expensive packages (with quartz windows through which ultraviolet (UV) radiation is used to erase the device) and the time it takes to erase them, on the order of 20 minutes. 

The next rung up the technology ladder was electrically erasable programmable read-only memories (EEPROMs or E 2PROMs). An E 2PROM cell is approximately 2.5 times larger than an equivalent EPROM cell because it comprises two transistors and the space between them (Figure 1-10). 

FIGURE 1-10 An E2PROM—cell.

The E2PROM transistor is similar to an EPROM transistor in that it contains a floating gate, but the insulating oxide layers surrounding this gate are very much thinner. The second transistor can be used to erase the cell electrically. E2PROMs first saw the light of day as computer memories, but the same technology was eventually applied to PLDs, which became known as electrically erasable PLDs (EEPLDs or E2PLDs).

FLASH can trace its ancestry to both EPROM and EEPROM technologies. The name “ FLASH ”was originally coined to reflect this technology’s rapid erasure times compared to EPROM. Components based on FLASH can employ a variety of architectures. Some have a single floating gate transistor cell with the same area as an EPROM cell, but with the thinner oxide layers characteristic of an E2PROM component. These devices can be electrically erased, but only by clearing the whole device or large portions thereof. Other architectures feature a two-transistor cell similar to that of an E2PROM cell, thereby allowing them to be erased and reprogrammed on a word-by-word basis.

—Technology Trade-offs—

● FLASH FPGAs are nonvolatile like antifuse FPGAs, but they are also reprogrammable like SRAM FPGAs. 

● FLASH FPGAs use a standard fabrication process like SRAM FPGAs and use lower power like antifuse FPGAs. 

● FLASH FPGAs are relatively fast.