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SRAM-based Devices

As seen in Chapter 1, the majority of FPGAs are based on the use of SRAM  configuration cells, which means that they can be configured over and over  again. The main advantages of this programming technology are that new  design ideas can be quickly implemented and tested, while evolving standards  and protocols can be accommodated relatively easily. Furthermore, when the  system is first powered up, the FPGA can initially be programmed to perform  one function such as a self-test or board/system test, and it can then be reprogrammed to perform its main task.

Another big advantage of the SRAM-based approach is that these devices  are at the forefront of technology. FPGA vendors can leverage the fact that many  other companies specializing in memory devices expend tremendous resources  on research and development (R & D) in this area. Furthermore, the SRAM cells  are created using exactly the same CMOS technologies as the rest of the device,  so no special processing steps are required in order to create these components.

Unfortunately, there’s no such thing as a free lunch. One downside of SRAM based devices is that they have to be reconfigured every time the system is powered up. This either requires the use of a special external memory device (which  has an associated cost and consumes real estate on the board) or of an on-board  microprocessor (or some variation of these techniques—see also Chapter 3).

Another consideration with regard to SRAM-based devices is that it can be  difficult to protect your intellectual property , or IP, in the form of your design.  This is because the configuration file used to program the device is stored in  some form of external memory.

On the bright side, some of today’s SRAM-based FPGAs support the  concept of bitstream encryption . In this case, the final configuration data is  encrypted before being stored in the external memory device. The encryption  key itself is loaded into a special SRAM-based register in the FPGA via its  JTAG port (see also Chapter 3). In conjunction with some associated logic, this  key allows the incoming encrypted configuration bitstream to be decrypted as  it’s being loaded into the device.

The command/process of loading an encrypted bitstream automatically disables the FPGA’s read-back capability. This means that you will typically use  unencrypted configuration data during development (where you need to use  read-back) and then start to use encrypted data when you move into production. (You can load an unencrypted bitstream at any time, so you can easily  load a test configuration and then reload the encrypted version.)

—Technology Trade-offs—

● The main downside to the encrypted bitstream scheme is that you require a  battery backup on the circuit board to maintain the contents of the encryption key register in the FPGA when power is removed from the system.  This battery will have a lifetime of years or decades because it need only  maintain a single register in the device, but it does add to the size, weight,  complexity, and cost of the board.

Unlike SRAM-based devices, which are programmed while resident in the  system, antifuse-based devices are programmed off-line using a special device  programmer. The proponents of antifuse-based FPGAs are proud to point to an  assortment of (not-insignificant) advantages:  

1. First, these devices are nonvolatile (their configuration data remains when  the system is powered down), which means that they are immediately  available as soon as power is applied to the system, and they don’t require  an external memory chip to store their configuration data, which saves the  cost of an additional component and saves real estate on the board.

2. Another noteworthy advantage of antifuse-based FPGAs is the fact that  their interconnect structure is naturally rad hard , which means they are  relatively immune to the effects of radiation. This is of particular interest in  the case of military and aerospace applications because the state of a configuration cell in an SRAM-based component can be “ flipped ” if that cell  is hit by radiation (of which there is a lot in space). By comparison, once  an antifuse has been programmed, it cannot be altered in this way.

3. Perhaps the most significant advantage of antifuse-based FPGAs is that  their configuration data is buried deep inside them, making it almost  impossible to reverse-engineer the design . By default, it is possible for  the device programmer to read this data out because this is actually how  the programmer works. As each antifuse is being processed, the device programmer keeps on testing it to determine when that element has been fully  programmed; then it moves on to the next antifuse. Furthermore, the device  programmer can be used to automatically verify that the configuration was  performed successfully (this is well worth doing when you’re talking about  devices containing 50 million plus programmable elements). Once the  device has been programmed, however, it is possible to set (grow) a special  security antifuse that subsequently prevents any programming data (in the  form of the presence or absence of antifuses) from being read out of the  device. Even if the device is decapped (its top is removed), programmed  and unprogrammed antifuses appear to be identical, and the fact that all of the antifuses are buried in the internal metallization layers makes reverseengineering close to impossible.  

   
   

Of course, the main disadvantage associated with antifuse-based devices is that  they are OTP, so once you’ve programmed one, its function is set in stone. This  makes these components a poor choice for use in a development or prototyping environment.  

—Technology Trade-offs—  
● Vendors of antifuse-based FPGAs may tout the fact that an antifuse-based  device consumes only 20 percent (approximately) of the standby power of an  equivalent SRAM-based component, that their operational power consumption  is also significantly lower, and that their interconnect-related delays are smaller. Also, they might casually mention that an antifuse is much smaller and thus  occupies much less real estate on the chip than an equivalent SRAM cell.

● They may neglect to mention, however, that antifuse devices also require  extra programming circuitry, including a large, hairy programming transistor for each antifuse.

● Also, antifuse technology requires the use of around three additional process steps after the main manufacturing process has been qualified. For this  (and related) reason, antifuse devices are always at least one—and usually  several—generations (technology nodes) behind SRAM-based components,  which effectively wipes out any speed or power consumption advantages  that might otherwise be of interest.  

E²PROM/FLASH-based Devices

E²  PROM- or FLASH-based FPGAs are similar to their SRAM counterparts  in that their configuration cells are connected together in a long shift-register style chain. These devices can be configured off-line using a device programmer. Alternatively, some versions are in-system programmable, or ISP, but  their programming time is about three times that of an SRAM-based component. However, they do have some advantages:

1. Once programmed, the data they contain is nonvolatile , so these devices  would be “ instant on ” when power is first applied to the system.

2. With regard to protection, some of these devices use the concept of a multibit key , which can range from around 50 bits to several hundred bits in  size. Once you’ve programmed the device, you can load your user-defined  key (bit-pattern) to secure its configuration data. After the key has been  loaded, the only way to read data out of the device, or to write new data  into it, is to load a copy of your key via the JTAG port (this port is discussed later in this chapter and in Chapter 3). The fact that the JTAG port  in today’s devices runs at around 20 MHz means that it would take billions  of years to crack the key by exhaustively trying every possible value.

3. Two-transistor E 2  PROM and FLASH cells are approximately 2.5 times the  size of their one-transistor EPROM cousins, but they are still way smaller  than their SRAM counterparts . This means that the rest of the logic can  be much closer together, thereby reducing interconnect delays .

On the downside, these devices require around five additional process steps  on top of standard CMOS technology, which results in their lagging behind  SRAM-based devices by one or more generations (technology nodes). Last but  not least, these devices tend to have relatively high static power consumption  due to their containing vast numbers of internal pull-up resistors.

Hybrid FLASH-SRAM Devices

Last but not least, there’s always someone who wants to add yet one more  ingredient to the cooking pot. In the case of FPGAs, some vendors offer esoteric  combinations of programming technologies. For example, consider a device  where each configuration element is formed from the combination of a FLASH  (or E²  PROM) cell and an associated SRAM cell.

In this case, the FLASH elements can be preprogrammed. Then, when the  system is powered up, the contents of the FLASH cells are copied in a massively parallel fashion into their corresponding SRAM cells. This technique  gives you the nonvolatility associated with antifuse devices, which means the  device is immediately available when power is first applied to the system. But  unlike an antifuse-based component, you can subsequently use the SRAM cells  to reconfigure the device while it remains resident in the system. Alternatively,  you can reconfigure the device using its FLASH cells either while it remains  in the system or off-line by means of a device programmer.