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Designing with Xilinx FPGAs Using Vivado

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Designing with Xilinx FPGAs Using Vivado

The motivation for writing this book came as we saw that there are many books that are published related to using Xilinx software for FPGA designs. Most of these books are targeted to a specifi c version of Xilinx tools—be it ISE or Vivado or for a specifi c device. Xilinx makes two major releases of Vivado each year. Each release introduces signifi cant new features and capabilities. Similarly, in each new device architecture, Xilinx makes signifi cant enhancements. Hence, books written on any specifi c version of the software (or device architecture) get outdated very quickly. Besides, Xilinx anyways publishes its own set of documents which are updated with each major release of Vivado or FPGA architecture. 

In this book, we have tried to concentrate on conceptual understanding of Vivado. These are expected to remain current through the current architecture of the tool chain. Our attempt has been that with a good conceptual understanding provided by this book, you will be able to understand the details provided in the user guides, which delve into the details of commands and options.

The Vivado software tool used for implementing a design on Xilinx’s FPGAs has a lot of possible ways to read in a design. A user could describe the design in the form of HDL or “C” or make use of Xilinx-provided IP or use a third-party IP or the user could use his/her own HDL or “C” code as an IP to be used in multiple designs. A user could also describe the design using still higher level of abstractions using IP Integrator or SysGen. A design could also potentially use different types of inputs (for different portions of the design). You can use this book to understand the inherent strengths of the various modes of design entry. You can then decide which mechanism would be most suited for portions of the design. For the exact commands and syntax, you should refer to Xilinx documents. Our book provides a list of reference materials. Depending on which specifi c capability you plan to use, you can refer to the corresponding reference material.

Besides being useful to somebody who is new to Xilinx tools or FPGAs, the book may be found useful for those users who are migrating from ISE to Vivado. Vivado is conceptually very different from ISE. While ISE was mostly using proprietary formats for most of the fl ow, Vivado has moved on to industry standard formats. Users who have been long-time ISE users sometimes fi nd it diffi cult to get vi used to Vivado. This book helps them get a good understanding of Vivado concepts, which should make it easier for them to transition to Vivado from ISE.

Though I’ve been involved in some of the user guides published by Xilinx, doing this book in my personal capacity allows me to deviate from the offi cial stand also, wherever I wanted to, and share my real opinion.☺ The most effective way to make use of this book is to not worry about reading the book from cover to cover. You can easily feel free to skip the chapters that deal with topics which your design does not have. 

Hyderabad, India Sanjay Churiwala

Acknowledgments

I would like to express my gratitude to several of my colleagues and friends— within Xilinx and outside—who agreed to write the chapters on their areas of expertise and also reviewed each other’s work. Each of these authors is highly knowledgeable in their respective areas. They took time out of their regular work to be able to contribute to this book.

I also thank my management chain at Xilinx, especially Arne Barras, Salil Raje, Victor Peng, and Vamsi Boppana—who were supportive of this work, even though this was being done in my personal capacity. I also thank the Xilinx legal/HR team, who provided me with the necessary guidance, permissions, and approvals to be able to complete this work, including usage of copyrighted material where relevant: Rajesh Choudhary, Lorraine Cannon Lalor, David Parandoosh, Fred Hsu, Cynthia Zamorski, and Silvia Gianelli. Amandeep Singh Talwar has been very helpful with fi gures and various aspects of the word processor. I often reached out to him, whenever I was having diffi culty on either of these two aspects. Shant Chandrakar and Steve Trimberger helped me with specifi c items related to FPGA architecture. There are many more who have been supporting this actively.

I also thank my many teachers, colleagues, and seniors who have been teaching me so many things—that I could understand Semiconductor, EDA, and now specifi - cally Xilinx FPGAs and Vivado. Over the last 23 years of professional experience in this fi eld, there are just too many of such people that I dare not even try to name some, for the fear that I would end up fi lling up too many pages just with these names.

I also thank my family members. My immediate family members obviously adjusted with the fact that instead of spending time with them, I was working on this book. However, my entire extended family has been highly encouraging, by expressing their pride very openly at my past books.

And, I’m especially thankful to Charles Glaser of Springer, who is ever supportive of me working on any technical book. For this book, I also thank Murugesan Tamilselvan of Springer who is working through the actual processes involved in publication. 

For me, writing continues to be a hobby that I cherish. And, once in a while, when I encounter somebody who identifi es me with one of my books, the fun just gets multiplied many times for me. To anybody who has done this, I want to give a big “thanks” for encouraging me.

  • XC2S200-5PQ208C

    Manufacturer:XILINX

  • FPGA Spartan-II Family 200K Gates 5292 Cells 263MHz 0.18um Technology 2.5V 208-Pin PQFP
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  • XC2S200-6FG256C

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  • FPGA Spartan-II Family 200K Gates 5292 Cells 263MHz 0.18um Technology 2.5V 256-Pin FBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

    RoHS: No RoHS

  • XC2S200-6PQ208C

    Manufacturer:XILINX

  • FPGA Spartan-II Family 200K Gates 5292 Cells 263MHz 0.18um Technology 2.5V 208-Pin PQFP
  • Product Categories: SCM, board

    Lifecycle:Active Active

    RoHS: No RoHS

  • XC3S1500-4FG320C

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  • FPGA Spartan-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 320-Pin FBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

    RoHS: No RoHS

  • XC3S1500-4FG676C

    Manufacturer:XILINX

  • FPGA Spartan-3 Family 1.5M Gates 29952 Cells 630MHz 90nm Technology 1.2V 676-Pin FBGA
  • Product Categories: FPGAs

    Lifecycle:Active Active

    RoHS: No RoHS

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