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VHDL is a description language for digital electronic circuits that is used in difierent levels of abstraction. The VHDL acronym stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. This means that VHDL can be used to accelerate the design process.
It is very important to point out that VHDL is NOT a programming language. Therefore, knowing its syntax does not necessarily mean being able to designing digital circuits with it. VHDL is an HDL (Hardware Description Language), which allows describing both asynchronous and synchronous circuits. For this purpose, we shall:
• Think in terms of gates and flip-flops, not in variables or functions.
• Avoid combinatorial loops and conditional clocks.
• Know which part of the circuit is combinatorial and which one is sequential.
Why to use an HDL?
• To discover problems and faults in the design before actually implementing it in hardware.
• The complexity of an electronic system grows exponentially. For this reason, it is very convenient
to build a prototype of the circuit previously to its manufacturing process.
• It makes easy for a team of developers to work together.
In particular, VHDL allows not only describing the structure of the circuit (description from more simple subcircuits), but also the specification of the functionality of a circuit using directives, in a similar way as most standard programming languages do.
The most important aim of an HDL is to be able to simulate the logical behavior of a circuit by means of a description language that has many similarities with software description languages.
Digital circuits described in VHDL can be simulated using simulation tools that reproduce the operation of the involved circuit. For this purpose, developers use a set of rules standardized by the IEEE, which explain the syntax of the language, as well as how to simulate it. In addition, there are many tools that transform a VHDL code into a downloadable file that can be used to program a reconfigurable device. This process is named synthesis. The way a given tool carries out the synthesis process is very particular, and it greatly differs from what other synthesis tools do.
For XilinxTMusers: In this manual we will use the free synthesis tool provided by XilinxTM(Xilinx ISE Web Pack), which can be obtained through the following URL: http:/www.xilinx.com/support/download/index.htm All the examples in this manual that may include any coding that is specific from the XilinxTMtool will be highlighted in a box like this one.
TIP: Throughout this manual, boxes like this one will be used to better highlight tips for an effcient programming in VHDL. These tips are a set of basic rules that make the simulation results independent of the programming style. Hence, these rules make the developed code synthesizable, so it can be easily implemented in any platform.