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Clocking in FPGA Designs
FPGAs are designed to be used with synchronous design techniques. As such, understanding clocking structures and their capabilities is vital to be able to realize a design. Poor understanding will create designs that are unreliable and diffifi cult to meet timing, while good understanding will create reliable designs and allow you to focus on resolving non-clocking issues.
FPGA clocking is not a diffifi cult subject to understand. Wherever you face a design decision, opt to prioritize clocking and keep the clocking as simple as possible. This simple rule will guide you well. Often decisions taken that do not give optimal clocking performance will result in delays to the project, board respins, etc.
FPGAs provide low skew clock routing. These are high load distribution networks. The network is fully buffered by design. It does not reduce in performance as you increase the load. One key progression in UltraScale FPGAs is to provide more clocking flfl exibility when compared to older FPGAs. There are many more available networks to use now.
Additionally, FPGAs provide PLLs/MMCMs that allow you to do frequency synthesis and phase shifting. These attributes allow you to interface to external components and generate internal clocks of almost any frequency up to the maximum operating range of the FPGA. This allows for effifi cient FPGA design as you can easily change the frequency at which the design operates to be optimal for the given FPGA and part of the design.
A typical FPGA design has many clock networks, as shown in Fig. 12.1 , because each of the following may have its own network:
• Each source synchronous interface coming into or leaving the FPGA
• Each transceiver interface
• Internal system FPGA clock network
• Low-speed clocking networks for control like high fanout processor control via
an AXI-Lite interface, external fl ash clocking
• Optional internal fast clock networks for conducting DSP operations
Most designs do not run at any single clock frequency. Design frequencies are normally dictated by:
• Bandwidth of incoming data
• Bandwidth of outgoing data
• Resource consumed by a particular function
The fifi rst two points are typically decided by the system. However, the third point is a design decision, in the sense that there might be multiple combinations of freq vs. utilization that would be possible. Generating different frequency clocks is easy in a FPGA. Running something faster will usually save resource. So, you can change frequency to save FPGA resource like DSP slices.
Wireless radio designs, for example, have parts that run at sweet spot frequency of 491 MHz. Usually it is only the DSP portions that run at this performance. This includes fifi lters, power monitors, DPD, and crest factor reduction. The designs have characteristics such as:
• Low load control paths.
• Point-to-point data paths.
• Design can be pipelined without issue.
• Data paths are typically small around 32 bits
Wired designs tend to have a lot of switching and wide data paths. Data paths can be 512/1024/2048 bits. These large data paths represent a challenge to the FPGA design software. You can help here by selecting a frequency that balances the diffifi culty and data path width. These designs tend to operate in the region of 300–350 MHz. For UltraScale+, there could be benefifi t in doubling the frequency to something like 600 MHz and halving the data width. Smaller data widths are easier to route for the FPGA software tools.
For other types of design, you should consider data path sizes , high fanout nonclock nets, and logic levels required. These are the typical factors that inflfl uence Fmax . Of course, faster device families and speed grades move the window.
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