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Recent advances in design tools have enabled a new approach to FPGA design, C-based design . Designing in C allows you to specify your designs at higher levels of abstraction than traditional RTL and obtain the productivity benefi ts of working at a higher level of abstraction: faster design capture, faster design verifi cation, faster design changes, and easier design reuse.
Figure 10.1 provides an overview of the C-based design fl ow. The key steps are as follows:
• C simulation verifi es that the C function gives the desired behavior.
• High-level synthesis ( HLS) is used to synthesize the C function into an RTL design which satisfi es the specifi ed performance, timing, and resource requirements.
• RTL verifi cation confi rms the output from HLS matches the functionality of the original C function.
• During IP integration, the RTL output from HLS is incorporated into an RTL design.
• RTL synthesis and Place & Route then create the bitstream used to program the FPGA.
The productivity benefi ts of a C-based design fl ow are achieved at different stages of the design fl ow. During the initial development, the primary productivity benefi t is provided by fast C simulation which allows you to quickly verify the intended functionality. For example, to simulate a full frame of HD video for a typi- cal video algorithm using C simulation typically takes less than a minute. Simulating the RTL design to perform the same function typically takes a day, if not longer.
Fig. 10.1 C-based design flow
Once the functionality of the C code has been confi rmed, HLS allows you to quickly create different RTL implementations from the same C source code, allow- ing you the time to fi nd the most optimal implementation which satisfi es the design requirements: in some cases it may be a fast design at the cost of size, and in other cases it may be a smaller design at the cost of speed (or any point in between).
Once the design is complete, HLS allows the same C code to be easily targeted to a different technology or to a different clock frequency or to a different set of perfor- mance characteristics, making design migration and evolution substantially easier.
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