TABLE OF CONTENTS

• Preface
• State-of-the-Art Programmable Logic
  • The Evolution of Programmable Logic
  • Current Applications for FPGAs
  • Application Level System Architectures
  • FPGA Architecture
  • System on Chip
  • System Level Functions
• Vivado Design Tools
  • Project vs. Non-project Mode
  • GUI, Command Line, and Tcl
  • Overview of Vivado GUI
• IP Flows
  • IP Catalog
  • IP Customization
  • IP Generation
  • Using IP in Your Design
  • IP Constraints
  • IP Upgrade Decisions
  • Simulation of IP
• Gigabit Transceivers
  • PLLs
  • Power Down
  • Loopback
  • Dynamic Reconfi guration Port (DRP)
  • Transmitter
  • Receiver
  • Integrated Bit Error Ratio Tester (IBERT)
• Memory Controllers
  • Getting Started
  • Calibration
  • Signal Integrity
  • DDR4 SDRAM
  • RLDRAM3
  • QDRIV
• Processor Options
  • Introduction
  • Computing on FPGAs
  • Processors on FPGAs
  • Tool Chains
  • Putting It All Together
• Vivado IP Integrator
  • Terminology
  • IPI Flow
  • Tcl Support
• SysGen for DSP
  • Designing in System Generator for DSP
  • Verifi cation of System Generator Design
  • Integrating System Generator Submodule in a System
• Synthesis
  • Designs Migrating from ASIC
  • Getting the Most of Device Primitives
  • Attributes / Directives to Control Synthesis Behavior
  • Synthesis vs. Simulation Mismatch: Common Cases
  • Synthesis Switches
  • Coding Styles for Improved QOR
  • Guidelines to Get Best Results Out of Synthesis
• C-Based Design
  • C Simulation
  • Arbitrary Precision Data Types
  • High-Level Synthesis
  • Interface Synthesis
  • Measuring Performance
  • Optimizing Your RTL
  • Optimization Methodology
  • A Productivity Data Point
  • RTL Verifi cation
  • RTL Integration
  • Tcl Support
• Simulation
  • Setting Up Design for Simulation
  • Simulation of Behavioral/RTL Model
  • Debugging
  • Combining C with HDL Using DPI
  • Generating SAIF File for Power Estimation
• Clocking
  • Choice of Clock Frequency
  • Number of Clocks
  • A Typical Clock Network
  • Optimizing Clock Networks to Improve Internal Timing
  • Optimizing Clock Networks for Interfaces
• Stacked Silicon Interconnect (SSI)
  • SSI Terminology
  • Design Partitioning
  • Pinout Considerations for SSI Designs
  • Partitioning Considerations
  • SSI Synthesis Techniques
  • SSI Implementation Flow
  • Examining SSI Results
  • Divide and Conquer
• Timing Closure
  • Generating Timing Reports
  • Timing Paths and Constraint Correctness
  • Timing Closure Techniques
• Power Analysis and Optimization
  • Xilinx Power Estimator (XPE)
  • Vivado Report Power
  • Vivado Power Optimization
• System Monitor
  • Overview of SYSMON
  • Evolution of SYSMON in Xilinx FPGA
  • Using the SYSMON in System Design
  • ADC Capabilities of SYSMON
  • Transfer Function of Various On-Chip Sensors
  • Controlling the SYSMON Operation
  • Operating Modes of SYSMON
  • Using SYSMON in Standalone Mode
  • Disabling the SYSMON
  • SYSMON Use Cases
• Hardware Debug
  • Debug Methodologies for FPGA Designs
  • Instrumenting the Design for Debug
  • Interacting with Debug Instrumentation
  • Board-Level Debugging
• Emulation Using FPGAs
  • Types of Emulators
  • Emulation Using FPGAs
  • Challenges in Emulation Using FPGAs
  • General Methodology
  • Instrumenting
• Partial Reconfi guration and Hierarchical Design
  • Partial Reconfi guration
  • Tandem and Field Update
  • Hierarchical Design (HD) Preservation
  • Isolation Design Flow