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Xilinx ® provides power-effi cient transceivers in their FPGA architectures. Table 4.1 shows the maximum line rate supported by various transceivers for seven-series and UltraScale architectures. The transceivers are highly confi gurable and tightly inte- grated with the programmable logic resources of the FPGA. Because of very high degree of confi gurability of these transceivers, Vivado also comes with GT Wizard , which you can use to instantiate the transceivers with the right settings and connec- tions. It is important to understand various characteristics of the transceivers. This will allow you to understand the system level implication of the confi guration options that you chose in the Wizard.
The reference clock input is terminated internally with 50 Ω on each leg to 4/5 MGTAVCC . Primitives such as IBUFDS_GTE2/IBUFDS_GTE3 are used to instantiate reference clock buffers. Advanced architectures like GTHE3/GTHE4 support output mode of operation. The recovered clock ( RXRECCLKOUT ) from any of the four channels within the same Quad can be routed to the dedicated reference clock I/O pins. This output clock can then be used as the reference clock input at a different location. The mode of operation cannot be changed during run time.
The reference clock output mode is accessed through one of the two primitives: OBUFDS_GTE3 and OBUFDS_GTE3_ADV . The choice of the primitive depends on your application.
Table 4.1 Maximum line rate supported by various transceivers
Fig. 4.1 QPLL and CPLL reference clock selection multiplexer
Figure 4.1 shows the detailed view of the reference clock multiplexer structure within a single GTHE3_COMMON primitive. The QPLL0REFCLKSEL and QPLL1REFCLKSEL ports are required when multiple reference clock sources are connected to this multiplexer. A single reference clock is most commonly used. In the case of a single reference clock, connect the reference clock to the GTREFCLK00 and GTREFCLK01 pins, and tie the QPLL0REFCLKSEL and QPLL1REFCLKSEL ports to 3′b001 .
Figure 4.1 also shows the reference clock multiplexer structure for the GTHE3_ CHANNEL primitive. The CPLLREFCLKSEL port is required when multiple refer- ence clock sources are connected to this multiplexer. For a single reference clock (which is the most common scenario), connect the reference clock to the GTREFCLK0 port and tie the CPLLREFCLKSEL port to 3′b001 . Vivado will handle the complexity of the multiplexers and associated routing.
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