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“Design for test” is a concept which means your chip is designed in such a way that testing it is easy. Test logic plays two roles. First, it helps debug a chip which has design flaws. Second, it can catch manufacturing problems. Both are particularly important for ASIC design because of the black box nature of ASICs where internal nodes are simply not accessible to you when there is a problem. These techniques are also applicable to CPLDs and FPGAs, many of which already have built-in test features. The following DFT techniques allow for better testing of a chip. While not all of these techniques need to be included in your design, those that are needed should be included at design time. DFT techniques should be taken into account during the design process rather than afterwards. Otherwise, circuits can be designed that are later found to be difficult, if not impossible, to test.
One important consideration that can be overlooked, is that test logic is intended to increase the testability and reliability of your chip. If test logic becomes too large, it can actually decrease reliability because the test logic can itself have problems which cause the chip to malfunction. A rule of thumb is that test circuitry should not make up more than 10% of the logic of the entire chip. Similarly, if you spend more than 10% of your time designing and simulating your test logic independently of the functionality of the chip, then you have more test circuitry than you need.
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