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Home > FPGA Technical Tutorials > Introduction to CPLD and FPGA Design > THE MASKED GATE ARRAY ASIC

THE MASKED GATE ARRAY ASIC

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An Application Specific Integrated Circuit, or ASIC, is a chip that can be  designed by an engineer with no particular knowledge of semiconductor physics  or semiconductor processes. The ASIC vendor has created a library of cells and  functions that the designer can use without needing to know precisely how  these functions are implemented in silicon. The ASIC vendor also typically  supports software tools that automate such processes as synthesis and circuit  layout. The ASIC vendor may even supply application engineers to assist the  ASIC design engineer with the task. The vendor then lays out the chip, creates  the masks, and manufactures the ASICs.

The gate array is an ASIC with a particular architecture that consists of rows and columns of regular transistor structures. Each basic cell, or gate,  consists of the same small number of transistors which are not connected. In  fact, none of the transistors on the gate array are initially connected at all. The  reason for this is that the connection is determined completely by the design  that you implement. Once you have your design, the layout software figures out  which transistors to connect. First, your low level functions are connected  together. For example, six transistors could be connected to create a D flipflop. These six transistors would be located physically very close to each other.  After your low level functions have been routed, these would in turn be  connected together. The software would continue this process until the entire  design is complete. This row and column structure is illustrated in Figure 1.

The ASIC vendor manufactures many unrouted die which contain the  arrays of gates and which it can use for any gate array customer. An integrated  circuit consists of many layers of materials including semiconductor material  (e.g., silicon), insulators (e.g., oxides), and conductors (e.g., metal). An  unrouted die is processed with all of the layers except for the final metal layers  that connects the gates together. Once your design is complete, the vendor  simply needs to add the last metal layers to the die to create your chip, using  photomasks for each metal layer. For this reason, it is sometimes referred to as  a Masked Gate Array to differentiate it from a Field Programmable Gate Array.

Masked Gate Array Architecture.png



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    Manufacturer:Xilinx

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  • Product Categories: FPGAs

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    Manufacturer:Xilinx

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    Manufacturer:Xilinx

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    RoHS: No RoHS

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    Manufacturer:Xilinx

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    RoHS:

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