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A decoder is a simple combinatorial block that converts one form of digital representation into another. Usually, a decoder takes a smaller representation and converts it into a larger one (the opposite of encoding). Typical examples are the decoding of an n-bit word into 2 n individual logic signals. For example a 3-8 decoder takes three logic signals in and decodes the value of one of the eight output signals (2 3 ) to the selected value. The symbol for such a decoder is given in Figure 25.1 with its functional behavior shown in the following table:
The VHDL for this decoder uses a simple VHDL construct similar to the if - else - end if form, except using the when - else syntax. If a signal is assigned a value when a condition is satisfied, then a single assignment can be made using the following basic pseudocode:
1 output <= value when condition;
This can be extended with else statements to cover a set of different conditions, thus:
1 output <= value1 when condition1 else
2 value2 when condition2 else
3 .
4 valuen when condition;
Finally, if there is a “catch all” condition, similar to the final else in an if - else - end if conditional statement in VHDL, then the final assignment would be added as follows:
Figure 25.1 3-8 decoder.
1 output <= value1 when condition1 else
2 value2 when condition2 else
3 .
4 valuen when conditionn else
5 valuedefault;
Using this approach, the 3-8 decoder can be simply implemented using the following VHDL:
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity decoder38 is
6 port (
7 s : in std_logic_vector (2 downto 0);
8 q : out std_logic_vector(7 downto 0)
9 );
10 end;
11
12 architecture simple of decoder38 is
13 begin
14 q <= "00000001" when s = "000" else
15 "00000010" when s = "001" else
16 "00000100" when s = "010" else
17 "00001000" when s = "011" else
18 "00010000" when s = "100" else
19 "00100000" when s = "101" else
20 "01000000" when s = "110" else
21 "10000000" when s = "111" else
22 "XXXXXXXX";
23 end;
The test bench for this decoder could be a simple look-up table of values, but in fact we could combine the clock and reset test bench from the counter example, and include a simple counter in the test bench to generate the signals input to the decoder as follows:
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 entity Decoder38Test is
6 end Decoder38Test;
7
8 architecture stimulus of Decoder38Test is
9 signal rst : std_logic := ’0’;
10 signal clk : std_logic:=’0’;
11 signal s : std_logic_vector(2 downto 0);
12 signal q : std_logic_vector(7 downto 0);
13
14 component decoder38
15 port(
16 s : in std_logic_vector(2 downto 0);
17 q : out std_logic_vector(7 downto 0)
18 );
19 end component;
20 for all : decoder38 use entity work.decoder38 ;
21
22 begin
23
24 CUT: decoder38 port map(s => s, q => q);
25 clk <= not clk after 1 us;
26 process
27 begin
28 rst<=’0’,’1’ after 2.5 us;
29 wait;
30 end process;
31
32 process(clk, rst)
33 variable count : unsigned(2 downto 0);
34 begin
35 if rst = ’0’ then
36 count := (others => ’0’);
37 elsif rising_edge(clk) then
38 count := count + 1;
39 end if;
40 s <= std_logic_vector(count);
41 end process;
42
43 end;
In Verilog, we can use similar techniques to select individual lines from a binary choice, except that we use a slightly different conditional assignment syntax using a case statement:
1 case (s)
2 3’h0: q = 8’b00000001;
3 .
4 default: q = 8’b00000000;
5 endcase
The resulting Verilog code is given as follows:
1 module decoder38(s, q);
2 output reg [7:0] q;
3 input [2:0] s;
4
5 always @(CharIn)
6 case (CharIn)
7 3’h0: HexOut = 8’b00000001;
8 3’h1: HexOut = 8’b00000010;
9 3’h2: HexOut = 8’b00000100;
10 3’h3: HexOut = 8’b00001000;
11 3’h4: HexOut = 8’b00010000;
12 3’h5: HexOut = 8’b00100000;
13 3’h6: HexOut = 8’b01000000;
14 3’h7: HexOut = 8’b10000000;
15 default: HexOut = 8’b00000000;
16 endcase
17 endmodule
In Verilog we can use a simple counter in a test bench to select each possibility in turn and then observe the output:
1 module decoder38_tb (
2 clk,
3 qout
4 );
5
6 input clk;
7 output [7:0] qout;
8
9 reg [2:0] s = 3’h0;
10
11 always @ (posedge clk)
12 begin
13 / Increment the counter
14 s <= s + 1;
15 end
16
17 / Decode the character into the LED segments
18 decoder38 decoder381(qout, s);
19
20 endmodule
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